Design of approach of IC

In CMOS integrated circuit design there is a trade-

off between static power consumption and technology
scaling. Recently, the power density has increased due to
combination of higher clock speeds, greater functional
integration, and smaller process geometries.
CMOS TESTING
• CMOS Testing
• Need for testing
• Test principles
• Design strategies for test
• Chip level test techniques
• System-level test techniques
• Layout design for improved testability
 CMOS Testing
 Testing is one of the most expensive parts of chips
• Logic verification accounts for > 50% of
design effort for many chips
• Debug time after fabrication has enormous
opportunity cost
• Shipping defective parts can sink a company

 Example: Intel FDIV( floating point division) bug

(1994)
• Logic error not caught until > 1M units shipped
• Recall cost $450M
 Need for Testing

The need of testing is to find out errors in the

application. The good reasons of testing are
1) Quality Assurance.
2) Verification and validating the
product/application before it goes live in the
market.
3) Defect free and user friendly.
4) Meets the requirements.
 Logic Verification
 Does the chip simulate correctly?
• Usually done at HDL level
• Verification engineers write test bench for HDL
» Can’t test all cases
» Look for corner cases
» Try to break logic design
 Ex: 32-bit adder
• Test all combinations of corner cases as inputs:
» 0, 1, 2, 231-1, -1, -231, a few random
numbers
 Good tests require ingenuity(originality)
 Silicon Debug
 Test the first chips back from fabrication
• If you are lucky, they work the first time
• If not…
 Logic bugs vs. electrical failures
• Most chip failures are logic bugs from inadequate
simulation
• Some are electrical failures
» Crosstalk
» Dynamic nodes: leakage, charge sharing
» Ratio failures
• A few are tool or methodology failures (e.g. DRC)
 Fix the bugs and fabricate a corrected chip
 Manufacturing Test
 A speck of dust on a wafer is sufficient to kill chip
 Yield of any chip is < 100%
• Must test chips after manufacturing before
delivery to customers to
only ship good parts
 Manufacturing testers are
very expensive
• Minimize time on tester
• Careful selection of test vectors
Manufacturing Failures
 Stuck-At Faults
 How does a chip fail?
• Usually failures are shorts between two
conductors or opens in a conductor
• This can cause very complicated behavior
 A simpler model: Stuck-At
• Assume all failures cause nodes to be “stuck-
at” 0 or 1, i.e. shorted to GND or VDD
• Not quite true, but works well in practice
Examples
Overview of VLSI Test Technology
• Design for Testability (DFT)
– Generally incorporated in design
– Goal: improve controllability and/or
observability of internal nodes of a chip or
PCB
• Three basic approaches
– Ad-hoc techniques
– Scan design
• Boundary Scan
– Built-In Self-Test (BIST)
 Design of Testability
• Ad-hoc DFT techniques
– Add internal test points (usually multiplexers) for
• Controllability
• Observability
– Added on a case-by-case basis
• Primarily targets “hard to test” portions of chip

Normal system Normal system

data 0 data 0
Internal Primary
Test data input node to be Internal node to output
1 be observed 1
controlled
Test mode select Test mode select
controllability test point observability test point
Observability & Controllability
 Observability: ease of observing a node by
watching external output pins of the chip
 Controllability: ease of forcing a node to 0 or 1 by
driving input pins of the chip
 Combinational logic is usually easy to observe and
control
 Finite state machines can be very difficult,
requiring many cycles to enter desired state
• Especially if state transition diagram is not
known to the test engineer
 Test Pattern Generation
 Manufacturing test ideally would check every
node in the circuit to prove it is not stuck.
 Apply the smallest sequence of test vectors
necessary to prove each node is not stuck.

 Good observability and controllability reduces

number of test vectors required for manufacturing
test.
• Reduces the cost of testing
• Motivates design-for-test
 Design for Test
 Design the chip to increase observability and
controllability
 If each register could be observed and controlled,
test problem reduces to testing combinational logic
between registers.
 Better yet, logic blocks could enter test mode
where they generate test patterns and report the
results automatically.
Scannable Flip-flops
 Design for Testability
• Built-In Self-Test (BIST)
– Incorporates test pattern generator (TPG) and
output response analyzer (ORA) internal to
design
• Chip can test itself
– Can be used at all levels of testing
• Device  PCB  system  field operation
Primary Inputs
0 Circuit Primary Outputs
Under
TPG 1 Test
Pass
BIST Mode ORA
Fail
THANK YOU