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MPMC - 3.1b 16 Bit Microprocessor - 8086 - PIN Diagram

The document describes the pin diagram and functions of various pins of the 8086 microprocessor. It has 40 pins and describes address, data, control, status and power pins. The pins are for memory and I/O operations, interrupts, bus handling and multiprocessing support.

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sestokurta
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9 views

MPMC - 3.1b 16 Bit Microprocessor - 8086 - PIN Diagram

The document describes the pin diagram and functions of various pins of the 8086 microprocessor. It has 40 pins and describes address, data, control, status and power pins. The pins are for memory and I/O operations, interrupts, bus handling and multiprocessing support.

Uploaded by

sestokurta
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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3.

1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

3.1b 16-bit Microprocessor: 8086 - Architecture –


Pin diagram

Module:2 Microprocessor Architecture and Interfacing: Intel x86


Course: BECE204L – Microprocessors and Microcontrollers
-Dr Richards Joe Stanislaus
Assistant Professor - SENSE
Email: [email protected]
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

Module:3 8086 Microprocessor 3 hours

• 8086 Microprocessor: Architecture and Basic configurations, System


design using 8086, Introduction to Multiprogramming, System Bus
Structure, Multiprocessor configurations, Coprocessor. Introduction
to ARM7, Intel I (i3, i5, i7) Series Processors.
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1. 8086 Microprocessor: pins


• 8086 was the first microprocessor to
be manufactured using
40 pin Dual inline Packing (DIP)
• 8086 is 16 bit microprocessor
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.1 Pins: MN/


• A set of 8086 pins change their functions,
but other pins have common functions in
both the modes.
• It can operate either in minimum mode or
in maximum mode depends on MN/MX’
pin.
• MN/MX’ = 5V, 8086 works in minimum
mode
• MN/MX’ = GND, it works in maximum
mode
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.2 Pins: GND, VCC, CLK


 Pin 40: VCC: 5V DC power supply at
VCC
Pin 1 and 20-: GND: Ground
This pin directs the extra current of the
microprocessor to ground.
 pin 19: CLK
It provides timing to the processor to
perform its operations
Frequency is different for different
versions namely, 5MHz, 8MHz, 10 MHz.
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.3 Pins: AD0-AD15


Pin 2 - 16 & 39: AD0 – AD15 
multiplexed Address and Data bus
 16lines of address and data are
multiplexed to reduce the number of lines
inside the IC.
Either address or data bus will be enable
from multiplexed bus
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.4 Pins: A16/S3 – A19/S6


 Pin 35 to 38 - A16/S3 , A17/S4, A18/S5, A19/S6
 Higher bit 4 address lines are multiplexed with
status signals
During memory operations, these pins act as
address bus and contain memory address of
instruction or data
I/O operations- these pins are low shows status of
processor.
S3 and S4 show which segment is currently
accessed by the microprocessor.

Extra segment
Stack segment
Code segment
Data segment
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.5 Pins: S7/


 Pin 34
 Bus handle enable informs about existence of
data on the bus D8-D15
This signal is low during the first clock
cycle, thereafter it is active.
Access allowed
0 0 Whole 16 bit
0 1 Odd byte to D8-D15
1 0 Even byte to D0-D7
1 1 No action
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.6 Pins: RD’, READY, RESET


 Pin 32: RD’ : Active low shows READ
operation

PIN 22: READY (Active high signal)


an acknowledgement signal from I/O and
memory devices that the data has been
transferred.
High  Indicates that the device is ready to
transfer; Low  Wait state

 Pin 21: RESET : used to reset the


processor and other devices connected to
the system.
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.7 Pins: INTR, NMI,


 Pin 18: INTR : Interrupt request
last clock cycle of every instruction is
checked in order to determine whether that
instruction is an interrupt or not

PIN 17: NMI (Non maskable interrupt)


Uncontrollable interrupt

 Pin 24: : Interrupt acknowledge


When an interrupt is received by the
microprocessor, generates INTA signal as a
response to interrupt.
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.8 Pins: TEST’, ALE,


 Pin 23: TEST’: wait signal
High: Processor wait in idle state
LOW: Execution is continued
PIN 25: ALE (Address latch enable)
there is a valid address available in the
address/data bus

 Pin 26: : Data enable


When low: the transceiver gets enabled
and it separates the data from the
multiplexed address and data bus.
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.9 Pins: DT/R’, M/IO’, WR’


 Pin 27: DT/R’: Data transmit/receive
Direction of data flow:
If DT/R’=1 (High) : Data is transmitted
If DT/R’=0 (Low) : Data is received
PIN 28: M/IO’ (Memory / input output)
If M/IO’=1 (High) : Perform memory operations
If M/IO’=0 (Low) : Perform IO operations
 PIN 29: WR’ (Write data to M/IO)
When WR’=0 Write data to memory or IO
based on M/IO’ pin 28 status.
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.10 Pins: HOLD, HLDA, LOCK’


 Pin 31: HOLD: Peripheral’s request
HOLD will be made 1 to inform processor that
peripheral devices are requesting the usage of
address / data busses
PIN 30: HLDA (Acknowledge Hold)
Processor enables HLDA as 1 to acknowledge
the HOLD signal.
 PIN 29: LOCK’ (Lock)
When program has Lock command, CPU is
locked indicating other processors not to
ask for bus from CPU
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.11 Pins: QS1 and QS0


 Pin 24, 25: QS1 QS0: status of
Instruction
QS QS0 Status
1
0 0 No operation
0 1 First byte of Opcode from queue
1 0 Empty the queue
1 1 Subsequent byte from the queue
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.12 Pins: S0’, S1’, S2’


 Pin 26-28: S2’, S1’, S0’: status of
OperationUsed by bus controller 8288 to
generate control signals and memory related
signals and I/O control signals
3.1b 16-bit Microprocessor: 8086 - Architecture – Pin diagram

1.13 Pins: RQ/GT0’, RQ/GT1’


 Pin 31,30: RQ/GT0’, RQ/GT1’
Request/Grant permission for usage of
address/data bus while in multiple
processor mode:
When received, CPU sends
acknowledgement signal

RQ/GT0 has higher priority than RQ/GT1.

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