MICROPROCESSOR

KCS-403

By: Anand Prakash Srivastava, Asst. Prof.

UNIT-II

CS&E Department , NTC,GZB

UNIT II: Contents
• Basic Programming concepts
• Instruction Format
• Data Transfer operations
• Arithmetic operations
• Logic Operations, Branch operation
• Writing assembly language programs
• Programming techniques: looping, counting and indexing
• Additional data transfer and 16 bit arithmetic instruction
• Logic operation: rotate, compare, counter and time delays
• 8085 Interrupts
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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Instruction Formats
• The Instruction Format of 8085 set consists of one, two and three byte
instructions.
• The first byte is always the opcode; in two-byte instructions the second
byte is usually data; in three byte instructions the last two bytes present
address or 16-bit data.
• For Example : MOV A, B

• For Example : MVI B, 02H.

• For Example : JMP, 6002H.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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INTRODUCTION

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 Data Transfer Operations
These operations simply COPY the data from the source to the destination.
The data in the source is not changed.

Foe eg: MOV, MVI, LDA/STA, LDAX/STAX ETC.

They transfer:
• Data between registers.
• Data Byte to a register or memory location.
• Data between a memory location and a register.
• Data between an I/O Device and the accumulator.
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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• This instruction copies the contents of the source register into the
destination register. (Contents of the source register are not altered).
• If one of the operands is a memory location, its location is specified by the
contents of the HL registers.
• Example: MOV B, A or MOV B, M

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The 8-bit data is stored in the destination register or memory.
• If the operand is a memory location, its location is specified by the
contents of the H-L registers.
• Example: MVI B, 60H or MVI M, 40H

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The contents of a memory location, specified by a 16- bit address in the
operand, are copied to the accumulator.
• The contents of the source are not altered.
• Example: LDA 2000H

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The contents of the designated register pair point to a memory location.
• This instruction copies the contents of that memory location into the
accumulator.
• The contents of either the register pair or the memory location are not
altered.
• Example: LDAX D

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• This instruction loads 16-bit data in the register pair.
• Example: LXI H, 2030 H

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• This instruction copies the contents of memory location pointed out by 16-bit
address into register L.
• It copies the contents of next memory location into register H.
• Example: LHLD 2030 H

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The contents of accumulator are copied into the memory location specified
by the operand.
• Example: STA 2000H

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The contents of accumulator are copied into the memory location specified by
the contents of the register pair.
• Example: STAX B

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The contents of register L are stored into memory location specified by the 16-
bit address.
• The contents of register H are stored into the next memory location.
• Example: SHLD 8500H

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The contents of register H are exchanged with the contents of register D.
• The contents of register L are exchanged with the contents of register E.
• Example: XCHG

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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This instruction loads the contents of H-L pair into SP.
Example: SPHL

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• The contents of L register are exchanged with the location pointed out by
the contents of the SP.
• The contents of H register are exchanged with the next location (SP + 1).
• Example: XTHL

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The contents of registers H and L are copied into the program counter (PC).
• The contents of H are placed as the high-order byte and the contents of L as
the low-order byte.
• Example: PCHL

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The contents of register pair are copied onto
stack.
• SP is decremented and the contents of high-
order registers (B, D, H, A) are copied into
stack.
• SP is again decremented and the contents of
low-order registers (C, E, L, Flags) are copied
into stack.
• Example: PUSH B

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The contents of top of stack are copied into
register pair.
• The contents of location pointed out by SP
are copied to the low-order register (C, E,
L, Flags).
• SP is incremented and the contents of
location are copied to the high-order
register (B, D, H, A).
• Example: POP H

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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The contents of I/O port are copied into accumulator.
Example: IN 80 H

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• The contents of accumulator are copied into the I/O port.
• Example: OUT 50H

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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2. Arithmetic Instructions
• These instructions perform the operations like:
• ◦ Addition
• ◦ Subtract
• ◦ Increment
• ◦ Decrement

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 Addition

• Any 8-bit number, or the contents of register, or the contents of memory

location can be added to the contents of accumulator.
• The result (sum) is stored in the accumulator.
• No two other 8-bit registers can be added directly.
• Example: The contents of register B cannot be added directly to the
contents of register C.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 ADD R
ADD M
Add register or memory to accumulator
• The contents of register or memory are added to the contents of accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is specified by H-L pair.
• Example: ADD B or ADD M

ADC R
ADC M
Add register or memory to accumulator with carry
• The contents of register or memory and Carry Flag (CY) are added to the contents of accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is specified by H-L pair. All flags are modified to reflect the
result of the addition.
• Example: ADC B or ADC M
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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EXERCISE: ADDITION

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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EXERCISE: ADDITION

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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EXERCISE: ADDITION WITH CARRY

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 ADI 8-bit data
Add immediate to accumulator
• The 8-bit data is added to the contents of accumulator.
• The result is stored in accumulator.
• All flags are modified to reflect the result of the addition.
• Example: ADI 45 H
ACI 8-bit data
Add immediate to accumulator with carry
The 8-bit data and the Carry Flag (CY) are added to the contents of accumulator.
The result is stored in accumulator.
All flags are modified to reflect the result of the addition.
Example: ACI 45 H
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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 DAD Reg. pair
Add register pair to H-L pair
• The 16-bit contents of the register pair are added to the contents of H-L
pair.
• The result is stored in H-L pair.
• If the result is larger than 16 bits, then CY is set.
• No other flags are changed.
• Example: DAD B or DAD D

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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EXAMPLE: DAD INSTRUCTION

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 Subtraction

• Any 8-bit number, or the contents of register, or the contents of memory

location can be subtracted from the contents of accumulator.
• The result is stored in the accumulator.
• Subtraction is performed in 2’s complement form.
• If the result is negative, it is stored in 2’s complement form.
• No two other 8-bit registers can be subtracted directly.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 SUB R
SUB M
Subtract register or memory from accumulator
• The contents of the register or memory location are subtracted from the contents of the accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is specified by H-L pair.
• All flags are modified to reflect the result of subtraction. Example: SUB B or SUB M
SBB R
SBB M
Subtract register or memory from accumulator with borrow
The contents of the register or memory location and Borrow Flag (i.e. CY) are subtracted from the contents of
the accumulator.
The result is stored in accumulator. If the operand is memory location, its address is specified by H-L pair.
All flags are modified to reflect the result of subtraction.
Example: SBB B or SBB M
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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 SUI 8-bit data
Subtract immediate from accumulator
• The 8-bit data is subtracted from the contents of the accumulator.
• The result is stored in accumulator.
• All flags are modified to reflect the result of subtraction.
• Example: SUI 05H
SBI 8-bit data
Subtract immediate from accumulator with borrow
The 8-bit data and the Borrow Flag (i.e. CY) is subtracted from the contents of the
accumulator.
The result is stored in accumulator.
All flags are modified to reflect the result of subtraction.
Example: SBI 45 H Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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EXAMPLE: SUI
SBI

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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Increment / Decrement

• The 8-bit contents of a register or a memory location can be

incremented or decremented by 1.
• The 16-bit contents of a register pair can be incremented or
decremented by 1.
• Increment or decrement can be performed on any register or a
memory location.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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INR R
INR M
Increment register or memory by 1 (EXAMPLE: INR B or INR M)

INX R
Increment register pair by 1
EXAMPLE: INX H or INX B or INX D

DCR R
DCR M
Decrement register or memory by 1
EXAMPLE: DCR B or DCR M
DCX R
Decrement register pair by 1
EXAMPLE: DCX H or DCX
Asst.Prof.
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B or
Anand Prakash DCXDepartment
Srivastava,CS&E D , NTC,GZ
EXAMPLE: INR/DCR/INX/DCX

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 3. Logical Instructions

• These instructions perform logical operations on data stored in registers,

memory and status flags.
• The logical operations are:
• ◦ AND
• ◦ OR
• ◦ XOR
• ◦ Rotate
• ◦ Compare
• ◦ Complement
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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 AND, OR, XOR

• Any 8-bit data, or the contents of register, or memory location can

logically have
• ◦ AND operation
• ◦ OR operation
• ◦ XOR operation with the contents of accumulator.
• The result is stored in accumulator.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 ANA R
ANA M
Logical AND register or memory with accumulator

• The contents of the accumulator are logically ANDed with the contents of
register or memory.
• The result is placed in the accumulator.
• If the operand is a memory location, its address is specified by the
contents of H-L pair.
• S, Z, P are modified to reflect the result of the operation.
• CY is reset and AC is set.
• Example: ANA B or ANA M.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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EXAMPLE: ANA R

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EXAMPLE: ANA M

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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ANI 8-bit data
Logical AND immediate with accumulator
Example: ANI 86H

ORA R
ORA M
Logical OR register or memory with accumulator
EXAMPLE: ORA B or ORA M
ORI 8-bit data
Logical OR immediate with accumulator
Example: ORI 86H.

XRA R
XRA M
Logical XOR register or memory with accumulator
Example: XRA B or XRA M

XRI 8-bit data

XOR immediate with accumulator
Example: XRI 86H Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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EXAMPLE: XRA M

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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Compare Any 8-bit data, or the contents of register, or memory location can be
compares for:
CMP R Equality
CMR M Greater Than
Less Than with the contents of accumulator.

• The result is reflected in status

flags

• CPI 8-bit data

(Compare immediate with
accumulator)

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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Rotate: Each bit in the accumulator can be shifted
either left or right to the next position.
• RLC
• Rotate accumulator left
• Each binary bit of the accumulator is rotated left by one position.
• Bit D7 is placed in the position of D0 as well as in the Carry flag.
• CY is modified according to bit D7.
• S, Z, P, AC are not affected.
• Example: RLC.

• RRC
Rotate accumulator right Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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Example: RLC/RRC

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 RAL
Rotate accumulator left through carry
• Each binary bit of the accumulator is rotated left by one position through the
Carry flag.
• Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least
significant position D0.
• CY is modified according to bit D7.
• S, Z, P, AC are not affected.
• Example: RAL.
RAR
Rotate accumulator right through carry
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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EXAMPLE: RAL

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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EXAMPLE: RAR

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 Complement
CMA/ CMC
STC
• The contents of accumulator can be complemented.
• Each 0 is replaced by 1 and each 1 is replaced by 0.
• No flags are affected.
• Example: CMA A=A’
CMC: The Carry flag is complemented.
No other flags are affected.
Example: CMC => c=c’

STC: The Carry flag is set to 1.

No other flags are affected.
Example: STC CF=1 Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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 4. BRANCH INSTRUCTIONS

• The branch group instructions allows the microprocessor to

change the sequence of program either conditionally or under
certain test conditions. The group includes,
• (1) Jump instructions,
• (2) Call and Return instructions,
• (3) Restart instructions

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The program sequence is transferred to the memory location specified by the
16-bit address given in the operand.
• Example: JMP 2034 H.

The program sequence is transferred to the

memory location specified by the 16-bit
address given in the operand based on the
specified flag of the PSW.
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
Example: JZ 2034 H. B
• The program sequence is CALL CONDITIONALLY
transferred to the memory
location specified by the 16-bit
address given in the operand.
• Before the transfer, the address of
the next instruction after CALL
(the contents of the program
counter) is pushed onto the stack.
• Example: CALL 2034H.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 The program sequence is RETURN CONDITIONALLY
transferred from the subroutine
to the calling program.
 The two bytes from the top
of the stack are copied into the
program counter, and program
execution begins at the new
address.
 Example: RET

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• The RST instruction jumps the control
to one of eight memory locations
depending upon the number.
• These are used as software instructions
in a program to transfer program
execution to one of the eight locations.
• Example: RST 1, RST 2 and so on….

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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5. Machine Control Instructions
• The control instructions control the operation of microprocessor.

No operation is performed.
The instruction is fetched and
decoded but no operation is
executed. The CPU finishes executing the current
Example: NOP instruction and halts any further execution.
An interrupt or reset is necessary to exit from
the halt state.
Example: HLT
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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• The interrupt enable flip-flop is set and all interrupts are enabled.
• No flags are affected.
• This instruction is necessary to re-enable the interrupts (except TRAP).
• Example: EI

The interrupt enable flip-flop is reset and all the interrupts except the
TRAP are disabled.
No flags are affected.
Example: DI Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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• This is a multipurpose instruction
and used to implement the 8085
interrupts 7.5, 6.5, 5.5, and serial
data output.
• The instruction interprets the
accumulator contents as shown in
figure:
• Example: SIM

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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• This is a multipurpose instruction
used to read the status of
interrupts 7.5, 6.5, 5.5 and read
serial data input bit.
• The instruction loads eight bits in
the accumulator with the
interpretations shown in figure:
• Example: RIM

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 ASSEMBLY LANGUAGE
PROGRAMMING

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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1. Store the data byte 32H into memory location 4000H.

Program 1:
MVI A, 32H ; Store 32H in the accumulator
STA 4000H ; Copy accumulator contents at address 4000H
HLT ; Terminate program execution

Program 2:
LXI H, 4000H ; Load HL with 4000H
MVI M, 32H ;Store 32H in memory location pointed by HL
register pair
HLT ;Terminate program execution
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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 2. Exchange the contents of memory locations 2000H
and 4000H.
Program 1:
LDA 2000H ;Get the contents of memory location 2000H into accumulator
MOV B, A ;Save the contents into B register
LDA 4000H ; Get the contents of memory location 4000Hinto accumulator
STA 2000H ;Store the contents of accumulator at address 2000H
MOV A, B ;Get the saved contents back into A register
STA 4000H ;Store the contents of accumulator at address 4000H

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 2. Exchange the contents of memory locations 2000H and 4000H. Contd…..

Program 2:
LXI H, 2000H ;Initialize HL register pair as a pointer to memory location
2000H.
LXI D, 4000H ;Initialize DE register pair as a pointer to memory location
4000H.
MOV B, M ;Get the contents of memory location 2000H into B register.
LDAX D ;Get the contents of memory location 4000H into A register.
MOV M, A ;Store the contents of A register into memory location 2000H.
MOV A, B ;Copy the contents of B register into accumulator.
STAX D ;Store the contents of A register into memory location
4000H.
HLT ;Terminate program execution.
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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3. Find the 2's complement of the number stored at memory location 4200H and
store the complemented number at memory location 4300H.

LDA 4200H ;Get the number

CMA ;Complement the number
ADI, 01 H ;Add one in the number
STA 4300H ;Store the result
HLT ;Terminate program execution

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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4. Add the contents of memory locations 4000H and 4001H and place the result in memory location
4002H.

LXI H 4000H ;HL points 4000H

MOV A, M ;Get first operand
INX H ;HL points 4001H
ADD M ;Add second operand
INX H ;HL points 4002H
MOV M, A ;Store result at 4002H
HLT ;Terminate program execution

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 THE STACK

• The stack is an area of memory identified by the programmer for temporary storage of
information.
• • The stack is a LIFO structure. – Last In First Out.
• • The stack normally grows backwards into memory.
• In other words, the programmer defines the bottom of the stack and the stack grows up
into reducing address range
• Given that the stack grows backwards into memory, it is customary to place the bottom
of the stack at the end of memory to keep it as far away from user programs as possible.
• • In the 8085, the stack is defined by setting the SP (Stack Pointer) register.
• LXI SP, FFFFH
• • This sets the Stack Pointer to location FFFFH (end of memory for the 8085).
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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SAVING INFORMATION ON THE STACK

• The 8085 provides two instructions: PUSH and POP for storing
information on the stack and retrieving it back.
• Information is saved on the stack by PUSHing it on.
• It is retrieved from the stack by POPing it off.
• Both PUSH and POP work with register pairs ONLY

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 OPERATION OF THE STACK

• During pushing, the stack operates in a “decrement then store” style.

• The stack pointer is decremented first, then the information is placed on
the stack.
• • During poping, the stack operates in a “use then increment” style. –
• The information is retrieved from the top of the the stack and then the
pointer is incremented.
• The SP pointer always points to “the top of the stack”.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 LIFO: LAST IN FIRST OUT

• The order of PUSHs and POPs

must be opposite of each other in
order to retrieve information back
into its original location.
• PUSH B
• PUSH D
• ...
• POP D
• POP B
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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PROGRAMMING TECHNIQUES: LOOPING,
COUNTING AND INDEXING

• A loop counter is set up by loading a register with

a certain value.
• Then using the DCR (to decrement) and INR (to
increment) the contents of the register are updated.
• A loop is set up with a conditional jump
instruction that loops back or not depending on
whether the count has reached the termination
count.
• The operation of a loop counter can be described
using the following flowchart:
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
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SAMPLE ALP FOR IMPLEMENTING A LOOP
USING DCR INSTRUCTION

MVI C, 15H
LOOP: DCR C
JNZ LOOP

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

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 USING A REGISTER PAIR AS A LOOP
COUNTER
• Using a single register, one can repeat a
loop for a maximum count of 255 times. The following is an example of a
• • It is possible to increase this count by loop set up with a register pair as
using a register pair for the loop counter the loop counter:
instead of the single register. LXI B, 1000H
• A minor problem arises in how to test for LOOP: DCX B
the final count since DCX and INX do not MOV A, C
modify the flags. ORA B
• However, if the loop is looking for when JNZ LOOP
the count becomes zero, we can use a
small trick by ORing the Asst.Prof.
two Anand
registers in
Prakash Srivastava,CS&E Department , NTC,GZ
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 5. Calculate the sum of series of numbers.
The length of series is in memory Program (a):
location 2200H and series itself begins LDA 2200H
from 2201H. MOV C,A
(a) Assume the sum to be 8 bit number, SUB A
so ignore carry. Store the sum at LXI H,
2300H. 2201H
BACK: ADD M
(b) Assume the sum to be 16 bit
INX H
number. Store the sum at memory
DCR C
locations 2300H & 2301H JNZ BACK
INX H
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B MOV M,A
 LDA 2200H
Program (b) MOV C,A
LXI H,2201H
SUB A
MOV B, A
BACK: ADD M
JNC NEXT
INR B
NEXT: INX H
DCR C
JNZ BACK
STA 2300H
MOV A, B
STA 2301H
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B HLT
6. WAP to move a block of data from location A000H to B000H. Assume block size is 10.

LXI H, A000H
LXI D, B000H
MVI C, 0AH
BACK: MOV A, M
STAX D
INX H
INX D
DCR C
JNZ BACK
HLT
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B
7. WAP to find the largest number in a block of data. The length of block is in memory location
2200H and the block itself begins from location 2201H. Store the maximum number in 2300H.

LDA 2200H
MOV C, A
XRA A
LXI H, 2201H
BACK: CMP M
JNC NEXT
MOV A, M
NEXT: INX H
DCR C
JNZ BACK
STA 2300H
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
HLT B
 8. Add the 16-bit number in memory locations 4000H and 4001H to the
16-bit number in memory locations 4002H and 4003H.

The most significant eight bits of PROGRAM:

the two numbers to be added are in
memory locations 4001H and LHLD 4000H ;Get first I6-bit number
4003H. XCHG ;Save first I6-bit
Store the result in memory locations number in DE
4004H and 4005H with the most LHLD 4002H ;Get second I6-bit number
significant byte in memory location in HL
4005H. DAD D ;Add DE and HL
SHLD 4004H ;Store I6-bit result in
memory
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B locations 4004H and 4005H.
9. Mask the lower nibble of an 8-bit number.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
10. WAP to arrange numbers in an array in
ascending order.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
 LXI H, 2000H
MOV B, M
BACK1: MOV C, M
MVI D,00H
INX H
BACK: MOV A,M
INX H
CMP A,M
JC NEXT
JZ NEXT
MOV D, M
MOV M,A
DCX H
MOV M, D
INX H
NEXT: DCR C
JNZ BACK
DCR B
JNZ BACK1
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B HLT
Flow Chart Symbols

• A program is a set of instructions arranged in the specific sequence to do the

specific task. It tells the microprocessor what it has to do.

• The programmer must “speak” to the processor in a language which processor can
understand is called Microprocessor Programming .

• The flow chart is a graphical tool that allows programmer to represent various
actions which are to be performed in proper sequence.

• The graphical representation is very useful for clear understanding of the

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B
FLOW CHART SYMBOLS
• Oval : It indicates start or stop operation.

• Arrow : It indicates flow with direction.

• Parallelogram : It indicates input/output operation.

• Rectangle : It indicates process operation.

• Diamond : It indicates decision making operation.

• Double sided Rectangle : It indicates execution of

pre-defined process (subroutine).

• Circle with alphabet : It indicates continuation.

• A: Any alphabet
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B
FLOW DIAGRAM TO FIND
COMPLEMENT OF A NUMBER

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
READ THE STATUS OF INPUT PORT1 AND READ THE
STATUS OF DATALINE D7 MASKING THE REMAINING BITS.
• IN 01H
• ANI 80H
• OUT 01H
• HLT

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
KEEP RADIO ON (CONNECTED TO D7 OF PORT0)
CONTINUOUSLY WITHOUT AFFECTING THE FUNCTION
OF OTHER APPLIANCE.
• IN 00H
• ORI 80H
• OUT 00H
• HLT

• ANI 7FH

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
 DELAYS

• Knowing how many T-States an instruction requires, and keeping in

mind that a T-State is one clock cycle long, we can calculate the time
using the following formula:
Delay = No. of T-States / Frequency

• For example a “MVI” instruction uses 7 T-States.

• Therefore, if the Microprocessor is running at 2 MHz, the instruction
would require 3.5 µSeconds to complete.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
DELAY CALCULATION
• General rule :-
If there is 1 byte instruction we will require minimum 4 T-states.
If there is 2 byte instruction we will require minimum 7 T-states.
If there is 3 byte instruction we will require minimum 10 T-states.

For opcode fetch: 4 T-states.

Read: 3 T-state.
Write: 3 T-state.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
 DELAY LOOPS

• We can use a loop to produce a certain amount of time delay in

a program.
• The following is an example of a delay loop:

MVI C, FFH ;7 T-States

LOOP: DCR C ;4 T-States
JNZ LOOP ;10 T-States
The first instruction initializes the loop counter and is executed only once
requiring only 7 T-States.
• The following two instructions form a loop that requires 14 T-States to
execute and is repeated 255 times
Asst.Prof.
B
until
Anand Prakash C becomes
Srivastava,CS&E 0.
Department , NTC,GZ
 DELAY CALCULATION

• We need to keep in mind though that in the last iteration of the loop, the
JNZ instruction will fail and require only 7 T-States rather than the 10.
• Therefore, we must deduct 3 T-States from the total delay to get an
accurate delay calculation.
• To calculate the delay, we use the following formula:
• Tdelay = TO + TL
• – Tdelay = total delay
• – TO = delay outside the loop
• – TL = delay of the loop
• TO is the sum of all delays outside the loop.
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B
 DELAY CALCULATION CONTD…

• Using these formulas, we can calculate the time delay for the previous
example:
• TO = 7 T-States – Delay of the MVI instruction
• TL = (14 X 255) - 3 = 3567 T-States
• 14 T-States for the 2 instructions repeated 255 times (FF 16 = 25510)
reduced by the 3 T-States for the final JNZ.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
 Nested Loops

• Nested loops can be easily setup in Assembly

language by using two registers for the two loop
counters and updating the right register in the
right loop.
• In the figure, the body of loop2 can be before or
after loop1.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
NESTED LOOP

• Instead (or in conjunction with) Register Pairs, a nested loop structure

can be used to increase the total delay produced.

MVI B,10H ;7 T-States

LOOP2: MVI C, FFH ;7 T-States
LOOP1: DCR C ;4 T-States
JNZ LOOP1;10 T-States
DCR B ;4 T-States
JNZ LOOP2Asst.Prof.
;10Anand
T-States
Prakash Srivastava,CS&E Department , NTC,GZ
B
 NESTED LOOP CONTD….

• The calculation remains the same except that the formula must be applied
recursively to each loop.
• – Start with the inner loop, then plug that delay in the calculation of the outer
loop.
• • Delay of inner loop
• – TO1 = 7 T-States
• • MVI C, FFH instruction
• – TL1 = (255 X 14) - 3 = 3567 T-States
• 14 T-States for the DCR C and JNZ instructions repeated 255 times (FF16 =
25510) minus 3 for the Asst.Prof.
finalAnand
B
JNZ
Prakash Srivastava,CS&E Department , NTC,GZ
 NESTED LOOP CONTD…..

• Delay of outer loop

• – TO2 = 7 T-States
• • MVI B, 10H instruction
• – TL1 = (16 X (14 + 3574)) - 3 = 57405 T-States
• • 14 T-States for the DCR B and JNZ instructions and 3574 T-States for
loop1 repeated 16 times minus 3 for the final JNZ.
• – TDelay = 7 + 57405 = 57412 T-States
• • Total Delay
• – TDelay = 57412 X 0.5 µSec = 28.706 mSec
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B
DELAY CALCULATION EXAMPLE
MVI B, FFH
LOOP: DCR B
JNZ LOOP
RET
• Here the first instruction will be executed once, it will take 7 T-states. DCR
C instruction takes 4 T-states. This will be executed 255 (FF) times. The
JNZ instruction takes 10 T-states when it jumps (It jumps 254 times),
otherwise it will take 7 T-States. And the RET instruction takes 10 T-States.
• 7 + ((4*255) + (10*254)) + 7 + 10 = 3584. So the time delay will be 3584 *
1/3µs = 1194.66µs. So when we need some small delay, then we can use
this technique with some other
Asst.Prof.
B
values
Anand Prakash in the
Srivastava,CS&E place
Department of FF.
, NTC,GZ
DELAY CALCULATION EXAMPLE

MVI B, FFH
L1: MVI C, FFH
L2: DCR C
JNZ L2
DCR B
JNZ L1
RET

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
 INTERRUPTS

• Interrupt is a process where an external device can get the attention of the
microprocessor.
• An interrupt is considered to be an emergency signal.
• The Microprocessor should respond to it as soon as possible.
• The process starts from the I/O device.
• The process is asynchronous.
• When the Microprocessor receives an interrupt signal, it suspends the
currently executing program and jumps to an Interrupt Service Routine
(ISR) to respond to the incoming interrupt.
• Each interrupt will mostAsst.Prof.
B
probably have itsDepartment
Anand Prakash Srivastava,CS&E own, NTC,GZ
ISR.
 CLASSIFICATION OF INTERRUPTS

• Interrupts can be classified into two types:

• Maskable (can be delayed) • Non-Maskable (can not be
delayed)
• Interrupts can also be classified into:
• • Vectored (the address of the service routine is hard-wired)
• • Non-vectored (the address of the service routine needs to be
supplied externally)

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
RESPONDING TO INTERRUPTS

• Responding to an interrupt may be immediate or delayed depending on

whether the interrupt is maskable or non-maskable and whether interrupts
are being masked or not.
• There are two ways of redirecting the execution to the ISR depending on
whether the interrupt is vectored or non-vectored.
• The vector is already known to the Microprocessor.
• The device will have to supply the vector to the Microprocessor

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
 8085 INTERRUPTS

• The 8085 has 5 interrupt inputs.

• The INTR input.
The INTR input is the only non-vectored
interrupt.
INTR is maskable using the EI/DI instruction
pair.
• RST 5.5, RST 6.5, RST 7.5 are all automatically
vectored.
RST 5.5, RST 6.5, and RST 7.5 are all
maskable.
• TRAP is the only non-maskable interrupt in the
8085 Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B
 VECTORED INTERRUPT

• An interrupt vector is a pointer to where the ISR is stored in memory.

• • All interrupts (vectored or otherwise) are mapped onto a memory area
called the Interrupt Vector Table (IVT).
• The IVT is usually located in memory page 00 (0000H - 00FFH).
• The purpose of the IVT is to hold the vectors that redirect the
microprocessor to the right place when an interrupt arrives.
• The IVT is divided into several blocks. Each block is used by one of the
interrupts to hold its “vector”

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
THE 8085 NON-VECTORED INTERRUPT
PROCESS

• 1. The interrupt process should be enabled using the EI instruction.

• 2. The 8085 checks for an interrupt during the execution of every
instruction.
• 3. If there is an interrupt, the microprocessor will complete the executing
instruction, and start a RESTART sequence.
• 4. The RESTART sequence resets the interrupt flip flop and activates the
interrupt acknowledge signal (INTA).
• 5. Upon receiving the INTA signal, the interrupting device is expected to
return the op-code of one of the 8 RST instructions.
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B
THE 8085 NON-VECTORED INTERRUPT
PROCESS

• When the microprocessor executes the RST instruction received from the
device, it saves the address of the next instruction on the stack and jumps to
the appropriate entry in the IVT.
• 7. The IVT entry must redirect the microprocessor to the actual service
routine.
• 8. The service routine must include the instruction EI to re-enable the
interrupt process.
• 9. At the end of the service routine, the RET instruction returns the execution
to where the program was interrupted.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
ISSUES IN IMPLEMENTING INTR
INTERRUPTS
How long must INTR remain high?
• – The microprocessor checks the INTR line one clock cycle before the last
T-state of each instruction.
• – The interrupt process is Asynchronous.
• – The INTR must remain active long enough to allow for the longest
instruction.
• – The longest instruction for the 8085 is the conditional CALL instruction
which requires 18 T-states.
• Therefore, the INTR must remain active for 17.5 T-states.
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B
 ISSUES IN IMPLEMENTING INTR
INTERRUPTS
How long can the INTR remain high?

• The INTR line must be deactivated before the EI is executed. Otherwise,

the microprocessor will be interrupted again.
• The worst case situation is when EI is the first instruction in the ISR.
• Once the microprocessor starts to respond to an INTR interrupt, INTA
becomes active (=0).
• Therefore, INTR should be turned off as soon as the INTA signal is
received.
Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B
ISSUES IN IMPLEMENTING INTR
INTERRUPTS
Can the microprocessor be interrupted again before the completion of
the ISR?
• As soon as the 1st interrupt arrives, all maskable interrupts are disabled.
• They will only be enabled after the execution of the EI instruction.
• Therefore, the answer is: “only if you allow it to”.
• If the EI instruction is placed early in the ISR, other interrupt may occur
before the ISR is done.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
The 8085 Maskable/Vectored Interrupts
• The 8085 has 4 Masked/Vectored interrupt inputs.
• RST 5.5, RST 6.5, RST 7.5
• • They are all maskable.
• • They are automatically vectored according to the
following table:

The vectors for these interrupt fall in between the vectors for the RST
instructions. That’s why they have names like RST 5.5 (RST 5 and a half).

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
The 8085 Maskable/Vectored Interrupt Process

• 1. The interrupt process should be enabled using the EI instruction.

• 2. The 8085 checks for an interrupt during the execution of every
instruction.
• 3. If there is an interrupt, and if the interrupt is enabled using the
interrupt mask, the microprocessor will complete the executing
instruction, and reset the interrupt flip flop.
• 4. The microprocessor then executes a call instruction that sends the
execution to the appropriate location in the interrupt vector table.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
 The 8085 Maskable/Vectored Interrupt Process

• 5. When the microprocessor executes the call instruction, it saves the

address of the next instruction on the stack.
• 6. The microprocessor jumps to the specific service routine.
• 7. The service routine must include the instruction EI to re-enable the
interrupt process.
• 8. At the end of the service routine, the RET instruction returns the
execution to where the program was interrupted.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
TRAP

• TRAP is the only non-maskable interrupt.

• It does not need to be enabled because it cannot be disabled.
• It has the highest priority amongst interrupts.
• It is edge and level sensitive. – It needs to be high and stay high to be
recognized.
• Once it is recognized, it won’t be recognized again until it goes low, then
high again.
• TRAP is usually used for power failure and emergency shutoff.

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
 INTERNAL INTERRUPT PRIORITY

• Internally, the 8085 implements an interrupt priority scheme.

• – The interrupts are ordered as follows:
• • TRAP
• • RST 7.5
• • RST 6.5
• • RST 5.5
• • INTR
• – However, TRAP has lower priority than the HOLD signal used for
DMA. Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ
B
INTERRUPT SUMMARY

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B
 THE END

Asst.Prof. Anand Prakash Srivastava,CS&E Department , NTC,GZ

B