Unit 6

Basic I/O, Memory R/W and

Interrupt Operations
Contents:
1. Memory read/write, input/output, read/write operation in 8085 microprocessor
based system

2. Direct memory access (DMA)

Introduction, advantage and application
DMA controller 8237 interfacing

3. Interrupt
8085 interrupt pins and interrupt priority
Maskable and non-maskable interrupts
Vector and polled interrupt

4. 8259 operation
Block diagram and explanation
Priority modes and other features
 Memory

Primary Secondary

Semi random
R/W Read only Serial access
access

EPROM Disks Magnetic Tape

Dynamic Masked ROM
Static RAM EEPROM Floppy CCd(Charged
RAM PROM
FLASH HDD Coupled Device)
CDROM
DVD
Performance of memory:
1. Access time (ta):
• Read access time: It is the average time required to read the unit of
information from memory.
• Write access time: It is the average time required to write the unit of
information on memory.
• Access rate (ra) = 1/ta

2. Cycle time (tc):

• It is the average time that lapses between two successive read operation .
• Cycle rate (rc)= bandwidth = 1/tc
Access modes of memory:
1. Random access: In random access mode, the ta is independent of the
location from which the data is accessed.

2. Sequential access: In that mode, the ta is dependent of the location form

which the data is accessed.

3. Semi random-access: the semi random access combines these two. For eg.
In magnetic disk, any track can be accessed at random. But the access within
the truck must be in serial fashion.
Speed
Memory size
Cost (per bit)
Access Time i.e. Slower
Capacity
Address decoding:
• Microprocessor is connected with memory and I/O devices via common
address and data bus.
• Only one device can send data at a time and other devices can only
receive that data.
• If more than one device sends data at the same time, the data gets garbled.
• In order to avoid this situation, ensuring that the proper device gets
addressed at proper time, the technique called address decoding is used.
• In address decoding method, all devices like memory blocks, I/O units etc.
are assigned with a specific address.
• The address of the device is determined from the way in which the address
lines are used to derive a special device selection signal known as chip
select (CS).
• If the microprocessor has to write or to read from a device, the CS signal to
that block should be enabled and the address decoding circuit must ensure
that CS signal to other devices are not activated.
Types of Address Decoding

A. Depending upon the no. of address lines used to generate chip select signal
for the device, the address decoding is classified as:
1. I/O mapped I/O
• In this method, a device is identified with an 8 bit address and operated by
I/O related functions IN and OUT for that IO/M =1. Since only 8 bit address
is used, at most 256 bytes can be identified uniquely. Generally low order
address bits A0-A7 are used and upper bits A8-A15 are considered don’t care.
Usually I/O mapped I/O is used to map devices like 8255A, 8251A etc.
2. Memory mapped I/O
• In this method , a device is identified with 16 bit address and enabled memory
related functions such as STA , LDA for which IO/M =0, here chip select
signal of each device is derived from 16 bit address lines thus total addressing
capability is 64K bytes. Usually memory mapped I/O is used to map
memories like RAM, ROM etc.
B. Depending on the address that are allocated to the device, the address
decoding are categorized in the following two groups.

1. Unique Address Decoding:

• If all the address lines on that mapping mode are used for address decoding
then that decoding is called unique address decoding. It means all 8-lines in
I/O mapped I/O and all 16 lines in memory mapped I/O are used to derive
signal. It is expensive and complicated.
• If A0 is high and A1- A7 are low and if IOW becomes low, the latch gets enabled.
• The data to the LED can be transferred in only one case and hence the device has
unique address of 01H.
Eg: Eight I/P switch interfacing at 53H. (01010011)
2. Non Unique Address decoding:
• If all the address lines available on that mode are not used in address decoding
then that decoding is called non unique address decoding.

• If A0 is low. Then latch gets enabled.

• Here A1-A7 is neglected that is any even address can enable the latch.
Direct Memory Access (DMA)
&
DMA Controllers
Direct Memory Access (DMA) & DMA Controllers
• It is a feature of a modern computer systems that allows certain hardware
subsystems to access main system memory(to read or write data to or from
memory) without microprocessor intervention (independent of the central
processing unit), allowing processor to do other work.
• It means DMA is a method of transferring data from the computer's RAM to
another part of the computer without processing it using (CPU).
• Most data that is input or output from your computer is processed by the CPU,
but some data does not require processing, or can be processed by another
device. In these situations, DMA can save processing time and is a more
efficient way to move data from the computer's memory to other devices.
• For example, a sound card may need to access data stored in the computer's
RAM, but since it can process the data itself, it may use DMA to bypass the
CPU. Video cards that support DMA can also access the system memory and
process graphics without needing the CPU.
Basic DMA Operation
During a block input byte transfer, the following sequence occurs as the data byte is sent from
the interface to the memory:
1. The interface sends the DMA controller a request for DMA service.
2. A Bus request is made to the HOLD pin (active High) on the processor and the controller
gains control of the bus.
3. A Bus grant is returned to the DMA controller from the Hold Acknowledge (HLDA) pin
(active High) on the processor.
4. The DMA controller places contents of the address register onto the address bus.
5. The controller sends the interface a DMA acknowledgment, which tells the interface to put
data on the data bus.
6. The data byte is transferred to the memory location indicated by the address bus.
7. The interface latches the data.
8. The Bus request is dropped, the HOLD pin goes Low, and the controller relinquishes the bus.
9. The Bus grant from the processor is dropped and the HLDA pin goes Low.
10. The address register is incremented by 1.
11. The byte count is decremented by 1.
12. If the byte count is non-zero, return to step 1, otherwise stop.
Timing diagram of DMA operation

• HOLD is sampled in any clocking cycle.

• When the processor recognizes the hold, it stops executing software and enters hold
cycles.
• HLDA becomes active to indicate the processor has placed its buses at high-impedance
state.
o as can be seen in the timing diagram, there are a few clock cycles between the time that
HOLD changes and until HLDA changes
• HLDA output is a signal to the requesting device that the processor has relinquished
control of its memory and I/O space.
Direct Memory Access Controller (DMAC) options for data transfer

The DMA Controller has several options available for the transfer of data. They are:

1) Cycle Steal:
A read or write signal is generated by the DMAC, and the I/O device either generates
or latches the data. The DMAC effectively steals cycles from the processor in order to transfer
the byte, so single byte transfer is also known as cycle stealing.

2) Burst Transfer:
To achieve block transfers, some DMAC's incorporate an automatic sequencing of the
value presented on the address bus. A register is used as a byte count, being decremented for
each byte transfer, and upon the byte count reaching zero, the DMAC will release the bus.
When the DMAC operates in burst mode, the CPU is halted for the duration of the data
transfer.
3) Hidden DMA
It is possible to perform hidden DMA, which is transparent to the normal operation
of the CPU. In other words, the bus is grabbed by the DMAC when the processor is not
using it. The DMAC monitors the execution of the processor, and when it recognizes the
processor executing an instruction which has sufficient empty clock cycles to perform a
byte transfer, it waits till the processor is decoding the op-code, then grabs the bus during
this time. The processor is not slowed down, but continues processing normally. Naturally,
the data transfer by the DMAC must be completed before the processor starts.
Advantages of DMA
1. Computer System performance is improved by direct transfer of data between memory and
I/O devices bypassing the processor
2. Processor is free to perform operation that donot use system buses.
3. Quick data transfer.

Disadvantages of DMA
In case of Burst mode of transfer, the processor is rendered inactive for longer period of time.

Application of DMA
4. Extensively used for computer-based data acquisition including streaming data to disk, real-
time screen data display and continuous data acquisition.
5. DMA is used in HDD in later version.
6. PC-based DMA technology, along with high-speed bus technology, is driven by data
storage, communications and graphics needs-all of which require the highest rates of data
transfer between system memory and I/O devices.
7. Data acquisition applications have the same needs and therefore can take advantage of the
technology developed for larger markets.
Interrupt-Operations
Interrupt
• Interrupt is signals send by an external device to the processor, to request the
processor to perform a particular task or work.
• Mainly in the microprocessor based system the interrupts are used for data
transfer between the peripheral and the microprocessor.
• Need for Interrupt: Interrupts are particularly useful when interfacing I/O
devices that provide or require data at relatively low data transfer rate.
Polling vs. Interrupt
• Polling the device usually means reading its status register every so often until
the device's status changes to indicate that it has completed the request.
• Polling means the CPU keeps checking a flag to indicate if something happens.
• An interrupt driven device driver is one where the hardware device being
controlled will cause a hardware interrupt to occur whenever it needs to be
serviced.
• With interrupt, CPU is free to do other things, and when something happens, an
interrupt is generated to notify the CPU. So it means the CPU does not need to
check the flag.
• Polling is like picking up your phone every few seconds to see if you have a call.
Interrupts are like waiting for the phone to ring.
• Interrupts win if processor has other work to do and event response time is not
critical.
Interrupt Operations
The interrupt driven I/O operation takes the following steps.
1. The I/O unit issues an interrupt signal to the processor for exchange of data between them.
2. The processor finishes execution of the current instruction before responding to the
interrupt.
3. The processor sends an acknowledgement signal to the device that it issued the interrupt.
4. The processor transfers its control to the requested routine called “Interrupt Service
Routine (ISR)” by saving the contents of program status word (PSW) and program
counter (PC).
5. The processor now loads the PC with the location of interrupt service routine and then
fetches the instructions. The result is transferred to the interrupt handler program.
6. When interrupt processing is completed, the saved register’s value are retrieved from the
stack and restored to the register.
7. Finally it restores the PSW and PC values from the stack.
The figure summarizes these steps.
• The processor pushes the flag
register on the stack, disables the
INTR input and does essentially an
indirect call to the interrupt service
procedure.
• An IRET function at the end of
interrupt service procedure returns
execution to the main program.
Interrupt Service Routine
• An interrupt service routine (ISR) is a software routine that hardware
invokes in response to an interrupt.
• ISRs examine an interrupt and determine how to handle it.
• ISR is responsible for doing the following things:
1. Saving the processor context
2. Acknowledging the interrupt
3. Restoring the processor context
Interrupt Vector

• An interrupt vector is a pointer to where the ISR is stored in memory.

• All interrupts (vectored or otherwise) are mapped onto a memory area
called the Interrupt Vector Table (IVT).

• The purpose of the IVT is to hold the vectors that redirect the
microprocessor to the right place when an interrupt arrives.
Interrupt structures:
There are mainly two ways of servicing multiple interrupts
• Polled interrupts
• Daisy chain (vectored) interrupts.
Polled interrupts
• Polled interrupts are handled by using software which is slower than hardware
(vectored) interrupts.
• Here the processor has the general (common) interrupt service routine (ISR)
for all devices.
• The priority of the devices is determined by the order in which the routine
polls each device.
• The processor checks the starting with the highest priority device.
• Once it determines the source of the interrupt, it branches to the service
routine for that device.
• Here several external devices are connected to a single interrupt line (INTR)
of the microprocessor.
• When INTR signal goes up, the processor saves the contents of PC and other
registers and then branches to an address defined by the manufactures of the
processor.
• The user can write a program at this address to find the source of the interrupt
by starting the polled from highest priority device.
Daisy chain (vectored) interrupt
• In polled interrupt, the time required to poll each device may exceed the time
to service the device through software.
• To improve this, the faster mechanism called vectored or daisy chain interrupt
is used.
• Here the devices are connected in chain fashion.
• When INTR pin goes up, the processor saves its current status and then
generates INTA signal to the highest priority device.
• If this device has generated the interrupt, it will accept the INTA; otherwise it
will push INTA to the next priority device until the INTA is accepted by the
interrupting device.
• When INTA is accepted, the device provides a means to the processor for
findings the interrupt address vector using external hardware.
• The accepted device responds by placing a word on the data lines which
becomes the vector address with the help of any hardware through which the
processor points to appropriate device service routine.
• Here no general interrupt service routine need first that means appropriate ISR
of the device will be called.
Interrupt priority:
• If the processor gets multiple interrupts, then we need to deal these interrupts
one at a time and the dealing approaches are:

a. Sequential processing of interrupts

• When user program is executing and an interrupt occurs, interrupts are disabled
immediately.
• After the interrupt service routine completes, interrupts are enabled before
resuming the user program and the processor checks to see if additional
interrupts have occurred.
b. Priority wise processing of interrupts:
Types of interrupt
1. External interrupts:
• These interrupts are initiated by external devices such as A/D converters and
classified on following types.
a. Maskable interrupt :
• It can be enabled or disabled by executing instructions such as EI and DI. In
8085, EI sets the interrupt enable flip flop and enables the interrupt process.
DI resets the interrupt enable flip flop and disables the interrupt.

b. Non-maskable interrupt:
• It has higher priority over maskable interrupt and cannot be enabled or
disabled by the instructions.
2. Internal interrupts:
• These are indicated internally by exceptional conditions such as overflow,
divide by zero, and execution of illegal op-code. The user usually writes a
service routine to take correction measures and to provide an indication in
order to inform the user that exceptional condition has occurred.
• These can also be activated by execution of TRAP instruction. This interrupt
means TRAP is useful for operating the microprocessor in single step mode
and hence important in debugging.
• These interrupts are used by using software to call the function of an operating
system. Software interrupts are shorter than subroutine calls and they do not
need the calling program to know the operating system’s address in memory.
Interrupt Processing in 8085
Types of Interrupts:
1. Software interrupts:
• The software interrupts are program instructions. These instructions are
inserted at desired locations in a program.
• The 8085 has eight software interrupts from RST 0 to RST 7. The vector
address for these interrupts can be calculated as follows.
• Interrupt number * 8 = vector address
• For RST 5; 5 * 8 = 40 = 28H
• Vector address for interrupt RST 5 is 0028H
Restart (RST) instruction

Interrupt Vector address

RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
2. Hardware interrupts
• An external device initiates the hardware interrupts and placing an
appropriate signal at the interrupt pin of the processor.
• If the interrupt is accepted then the processor executes an interrupt service
routine.
• The 8085 has five hardware interrupts
Programmable Interrupt Controller (PIC) -8259A
• 8259 is Programmable Interrupt Controller (PIC)
• It is a tool for managing the interrupt requests.
• 8259 is a very flexible peripheral controller chip:
• PIC can deal with up to 64 interrupt inputs.
• interrupts can be masked
• various priority schemes can also be programmed.
• Originally (in PC XT) it is available as a separate IC
• Later the functionality of (two PICs) is in the motherboards chipset.
• In some of the modern processors, the functionality of the PIC is built in.
Operation:

1. The IRR stores the requests.

2. The priority resolver checks three registers: the IRR for interrupt requests, the IMR for
masking bits, and the ISR for the interrupt request being served. It resolves the priority and
sets the INT high when appropriate.

3. The MPU acknowledges the interrupt by sending INTA.

4. After the INTA is received, the appropriate priority bit in the ISR is set to indicate which
interrupt level is being served, and the corresponding bit in the IRR is reset to indicate that the
request is accepted. Then, the op-code for the CALL instruction is placed on the data bus.

5. When the MPU decodes the CALL instruction, it places two or more INTA signals on the
data bus.
6. When 8259A receives the second INTA, it places the low-order byte of the CALL address
on the data bus. At the third INTA, it places the high-order byte on the data bus. The CALL
address is the vector memory location for the interrupt: this address is placed in the control
register during the initialization.

7. During the third INTA pulse, the ISR bit is reset either automatically (Automatic-End-of-
Interrupt-AEOI) or by a command word that must be issued at the end of the service routine
(End-of-Interrupt-EOI). This option is determined by the initialization command word
(ICW).

8. The program sequence is transferred to the memory location specified by the CALL
instruction.