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Lecture 8

The document discusses field effect transistors and junction field effect transistors. It describes the construction and operation of JFETs, including how applying different voltages to the gate, drain, and source terminals affects the current flow. Key aspects covered include the high input impedance of FETs, the depletion region mechanism of voltage control in JFETs, and defining characteristics such as pinch-off voltage and maximum drain current.

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24 views

Lecture 8

The document discusses field effect transistors and junction field effect transistors. It describes the construction and operation of JFETs, including how applying different voltages to the gate, drain, and source terminals affects the current flow. Key aspects covered include the high input impedance of FETs, the depletion region mechanism of voltage control in JFETs, and defining characteristics such as pinch-off voltage and maximum drain current.

Uploaded by

pratikdash9938
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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College of Engineering stage / second

Dept. of the electrical power and Machine Date: Mon


Subject/ ELECTRONIC! Time/ 2 hours

Field Effect Transistor Introduction


The field-effect transistor (FET) is a three-terminal device used for a variety of applications. Although there are important differences
between the FET and BJT transistors types of devices, also many similarities. The primary difference between the two types of transistors
is the fact that the BJT transistor is a current-controlled device as depicted in Fig.1a, while the JFET transistor is a voltage-controlled
device as shown in Fig.1b. In other words, the current IC in Fig.1a is a direct function of the level of IB. For the FET the current I will be a
function of the voltage VGS applied to the input circuit as shown in Fig.1b.

Fig.5: (a) Current-controlled and (b) voltage-controlled amplifiers.

• One of the most important characteristics of the FET is its high input impedance.
Two types of FETs will be introduced in this chapter (chapter 5): the junction field-effect transistor (JFET) and the metal-oxide-
semiconductor field-effect transistor (MOsFET)

Assist. Lecturer: Mohammed.H.Ali


College of Engineering stage / second
Dept. of the electrical power and Machine Date: Mon
Subject/ ELECTRONIC! Time/ 2 hours

CONSTRUCTION AND CHARACTERISTICS OF JFETs

The basic construction of the n-channel JFET is shown in Fig.2. The top of the n-type channel is connected through an ohmic contact to a
terminal referred to as the drain (D), while the lower end of the same material is connected through an ohmic contact to a terminal
referred to as the source (S). The twop-type materials are connected together and to the gate (G) terminal. In essence, therefore, the drain
and source are connected to the ends of the n-type channel and the gate to the two layers of p-type material.

Assist. Lecturer: Mohammed.H.Ali


College of Engineering stage / second
Dept. of the electrical power and Machine Date: Mon
Subject/ ELECTRONIC! Time/ 2 hours

Fig.3: Water analogy for the JFET control mechanism.


The drain and source terminals are at opposite ends of the ^-channel as introduced in Fig.2 because the terminology is defined for electron
flow.
VGS = 0 V, VDS Some Positive Value
In Fig.4, a positive voltage VDS has been applied across the channel and the gate has been connected directly to the source to establish the
condition VGS = 0V. The result is a gate and source terminal at the same potential and a depletion region in the low end of each p-material
similar to the distribution of the no-bias conditions of Fig.2. The instant the voltage V DD (= VDS) is applied, the electrons will be drawn
to the drain terminal, establishing the conventional current I D with the defined direction of Fig.4. The path of charge flow clearly reveals
that the drain and source currents are equivalent (I D = IS).

Assist. Lecturer: Mohammed.H.Ali


College of Engineering
Dept, of the electrical power and Machine
Subject/ ELECTRONIC!
stage / second
Date: Mon
Time/ 2 hours

;he VGS = 0 V and VDS >0 V.

Assist. Lecturer: Mohammed.H.Ali


College of Engineering stage / second
Dept. of the electrical power and Machine Date: Mon
Subject/ ELECTRONIC! Time/ 2 hours

Assist. Lecturer: Mohammed.H.Ali


College of Engineering stage / second
Dept. of the electrical power and Machine Date: Mon
Subject/ ELECTRONIC! Time/ 2 hours

Fig.6: Pinch-off (VGS = 0 V, VDS = VP).

In essence, therefore, once VDS = VP the JFET has the characteristics of a current source. As shown in Fig.7, the current is fixed at ID =
IDSS, but the voltage VDS (for levels > VP) is determined by the applied load.
IDSS is the maximum drain current for a JFET and is defined by the conditions V GS = 0 V and VDS> \VF\.

Assist. Lecturer: Mohammed.H.Ali


College of Engineering stage / second
Dept. of the electrical power and Machine Date: Mon
Subject/ ELECTRONIC! Time/ 2 hours

Fig. 7: Current source equivalent for VGS = 0 V, VDS >VP


VGS > 0 V

The level of VGS that results in ID = 0 mA is defined by VGS = VP, with VP being a negative voltage for n-channel devices and a
positive voltage for p-channel JFETs

Fig.8: ^-Channel JFET characteristics with IDSS = 8 mA and VP =4 V.

Assist. Lecturer: Mohammed.H.Ali

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