Programmable Interrupt

Controller
Introduction - I/O interface
The 8259A PIC

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 I/O Interface [contd.]
• I/O involves transfer to/from peripheral devices
from/to data bus of CPU
– E.g. data transfer to CRT, from keyboard to/from HD,
to/from modem to another comp
• I/O operations fall into one of the following types:
– Programmed I/O: CPU polls peripherals to check if
I/O is needed
– Interrupt I/O: peripheral sends an interrupt request to
CPU for I/O
– DMA: peripheral writes directly to memory

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 Interrupt I/O
• Interrupts can be used for variety of applications
• HW interrupts are very efficient in handling I/O
devices
• Each of these requires separate input
• NMI – reserved for most urgent type
• INTR – for “normal” interrupts
• For multiple interrupt inputs – use priority
interrupt controller (PIC)
• 8259A: commonly used PIC

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 Interrupt priority
• Interrupt priorities
– When different types of interrupt (SW, NMI,
INTR) occur at the same time, the one with
highest priority is handled first
– Order of priority:

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 Interrupt priority
• If several INTRs are generated from different
peripherals simultaneously:
– Decide priority and send INTA to the highest
– Two different methods can be used to establish
priority of interrupt requests (IRs):
• Polling (and daisy chaining)
• Interrupt priority management HW
– Polling: involves asking each peripheral in a
predetermined order whether it needs attention from
the microprocessor
• The first peripheral which responds “yes” is served
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 Polling and daisy chaining
– Daisy chaining: a method of implementing
polling scheme by hardware
• INTA signal passes along a series of peripherals
from one to next only if peripheral is not requesting
interrupt
• Hence the first peripheral in the daisy chain has
the highest priority and the last – the lowest
• Disadvantage: limited no of devices could be
chained b/c of delays in passing INTA through the
chain

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 Programmable interrupt controller (PIC 8259)

– PIC (8259A) is usually used in practical

systems to determine priority of interrupts
– 8259A assigns priority of up to 8 vectored
interrupt sources to be connected to INTR pin
– It can be cascaded (1 master, 8 slaves) to
provide 64 interrupt lines
• Pin outs:
– 8259A is a 28 pin

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 PIC 8259
• 8259A pin outs
– D0-D7: connected to
data bus to allow
programming
– IR0-IR7: 8 interrupt
inputs
– CAS0-CAS2: cascade
lines (used in multiple
systems)
– SP/EN’: data buffer
enable o/p (buffered
mode) or i/p to program
it as master/slave
– A0: selects different
command words
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 PIC 8259
• Usually IR0 has the highest priority & IR7
the least
• Fully nested interrupts are supported if bit
4 of ICW1 is set

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 8086 interrupt response
• If IF is set & INTR receives high, 8086 will:
– Send out 2 intr ack pulses on INTA’ pin to 8259A
INTA’ pin to tell to send the desired INT type on bus
– Multiply the interrupt type it receives by 4 to produce
address in int vector table (IVT)
– Push flags on the stack
– Clear IF and TF
– Push return address on the stack
– Get starting address of ISR from IVT and load it in
CS:IP
– Execute ISR

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PIC 8259 internal architecture

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 PIC 8259A internal architecture
• Data bus buffer: bidirectional 3 state buffer thru which
MP can access 8259A’s internal registers (wr cw/rd sw)
• R/W’ logic: accepts I/P RD’, WR’, A0 & CS to control
direction, timing and source/destination of data transfer
• IMR: used to mask out individual interrupt request input
(IR0-IR7)
• IRR: stores the current status of the interrupt request input
• Priority resolver: determines priority of the active
interrupt inputs
• ISR: stores interrupt level that is presently being served
• Cascade buffer: provides interface between master and
slave 8259A. Each slave has ID code stored here
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 Programming 8259A
– Programmed by sending:
• initialization command words (ICWs)
• operational command words (OCWs)
– ICW commands: to load internal control
registers
– OCW commands: to initiate variations in the
basic operating modes defined by ICWs
– ICW and OCW cmds – issued by OUT
instruction

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 8259A initialization
• ICW sending order:

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 8259A ICW formats
• ICW1: used to program the basic operation of 8289A

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 8259A ICW formats
• ICW1:
– A0 – not part of the CW, tells the internal
address that the CW must be sent to
– D0 (ICW4) – tells whether ICW4 is needed or
not. It is needed if device is used with 8086
system
– D1(SNGL) – single or cascaded mode
– D2 – =‘X’ when used with 8086 system
– D3 – whether level/edge triggered mode
– D4=1 (for 8086), D5, D6, D7 = ‘X’
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 8259A ICW formats
• ICW2:
– Used to tell the 8259A type number (base) to
send in response to intr signal on IR0 input
– For other IR inputs, 8289A will automatically
add no of IR input to this base no
– E.g.Type 32d is the lowest type no available
to use. This is sent as type to 8086 in
response to IR0, and type 33d to IR1, …
– In any ICW2 to be sent to 8259A, the lowest 3
bits must always be 0 b/c it automatically
supplies them to correspond to no of IR i/p
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 8259A ICW formats
• ICW2 format

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 8259A ICW formats
• ICW3 (master): used only when ICW1 specifies that
system operated in cascade mode;
– Used to indicate where the slave is connected to the master

Ans: 04H

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 8259A ICW formats
• ICW3 (slave)

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 8259A ICW formats
• ICW4:
– Used if IC4 bit of ICW1 = 1(neglected otherwise)
• i.e. D0 = 1 for 8086 system
– D1 – automatic end of interrupt
• If D1=1, 8289A will automatically reset the ISReg bit
for the int i/p being responded to
– M/S – master/slave: M/S=1 => master
– SFNM – if BUF=1, buffered mode is selected
• Allows master to accept request on a (master) IR input
that is already in service
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 8259A ICW formats
• ICW4 format:

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8259A ICW formats

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 8259A OCW formats
• OCW1:
– Sent to unmask any IR input to be responded to
– e.g. to unmask IR2 and IR3: OCW = 111110011

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 Reading assignment:
• 8259A:
– OCW1: to reset a bit in the ISReg
– OCW2: to select a register to be read, …

• Programmable Timer/Counter (8254A)

• Keyboard and display controller (8279)
• A/D, D/A converters?

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Next class:

USART

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