Sequential Logic

Sequential Circuits
 The outputs of the circuit will depends upon the present
inputs as well as on the sequence of the previous outputs of
the circuits.
 It is basically combination of combinational circuit and
memory unit.

2
 Sequential Circuits
Combinational Circuit Sequential Circuit
Logic gates are the basic Flip flops are the basic
elements used. elements used.
It consists of input, output It consists of input, output
variables and logic gates variables ,logic gates inter
inter connection. connection and memory
unit.
No memory unit present. Present
Outputs can be calculated Output depends upon
from the function with present inputs as well as past
input. outputs.
Input triggers the Clock pulse and previous
combinational circuit. outputs triggers the S C

3
 Latch
Latch is storage device. A latch is constructed from the
cross coupled NAND or NOR gates.
The outputs of Latch are compliment of each other.
i.e. Q≠Q’
 SR Latch
S R Q Q’
0 0 1 1
0 1 0 1
1 0 1 0
1 1 Not used Not used

SR latch using NOR gates

Case I
When S = 1 and R =0; Q = 1 and Q’ = 0

When S = 0 and R = 0; Q = 1 and Q’ = 0 ( Memory) A B F

Case II
0 0 1
When S = 0 and R = 1; Q = 0 and Q’ = 1 0 1 0
When S = 0 and R = 0; Q = 0 and Q’ = 1 (Memory) 1 0 0
Case III 1 1 0
When S = 1 and R = 1; Q = 0 and Q’ = 0 [Not Used]
 SR Latch
S
Q

Q’
R

SR latch using NAND gates

S R Q Q’ A B F
0 0 Not used Not used 0 0 1
0 1 1 0 0 1 1
1 0 0 1 1 0 1
1 1 Memory Memory 1 1 0
 Clock Pulse and Triggering
Varying Signal that triggers or control the operation of
Flip flops.

Triggering Methods
Level Triggering
Edge Triggering
 SR Flip Flop

Clk

S* R* Q Q’
0 0 Not used Not used
0 1 1 0
1 0 0 1
1 1 Memory Memory

TT of SR latch using NAND

 TT of SR flip flop

Clk S R Q Q’
0 x x Mem Mem
1 0 0 Mem Mem
1 0 1 0 1
1 1 0 1 0
1 1 1 Invalid Invalid
 SR Flip Flop
Clk S R Q n+1 Qn S R Q n+1
0 x x Qn
0 0 0 0
1 0 0 Qn
0 0 1 0
1 0 1 0
0 1 0 1
1 1 0 1
0 1 1 x
1 1 1 Not used
1 0 0 1
Truth table of SR flip flop 1 0 1 0
Qn Q n+1 S R 1 1 0 1
1 1 1 x
0 0 0 x
Characteristics table of SR flip flop
0 1 1 0
Qn+1 = QnR’ + S
1 0 0 1
1 1 x 0

Excitation table of SR flip flop

 D Flip Flop
S

Clk S R Q n+1
0 x x Qn Clk D Qn+1
1 0 0 Qn 0 x Qn
1 0 1 0 1 0 0
1 1 0 1 1 1 1
1 1 1 Not used
TT of D flip flop
TT of SR flip flop
 D Flip Flop
Clk D Qn+1 Qn D Qn+1
0 x Qn 0 0 0
1 0 0 0 1 1
1 1 1 1 0 0
1 1 1
TT of D flip flop
Characteristics of D flip flop

Qn Qn+1 D Qn+1 = D
0 0 0
0 1 1
1 0 0
1 1 1
Excitation of D flip flop
 JK Flip Flop

CLK S R Qn+1 CLK J K Qn+1

0 X X Qn 0 X X Qn
1 0 0 Qn 1 0 0 Qn
1 0 1 0 1 0 1 0
1 1 0 1 1 1 0 1
1 1 1 Invalid 1 1 1 Q’n Toggling
T.T for S-R Flip-Flop T.T for J-K Flip-Flop
JK Flip Flop
 T Flip Flop

CLK J K Qn+1
0 X X Qn CLK T Qn+1
1 0 0 Qn 0 X Qn
1 0 1 0 1 0 Qn
1 1 0 1 1 1 Q’n
1 1 1 Qn ’ T.T for T Flip-Flop
T.T for J-K Flip-Flop
 T Flip Flop
CLK T Qn+1 Qn T Qn+1
0 X Qn 0 0 0
1 0 Qn 0 1 1
1 1 Qn ’ 1 0 1

T.T for T Flip-Flop 1 1 0

Characteristics table for T Flip-Flop

Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Table for T Flip-Flop
 JK Flip Flop
CLK J K Qn+1
0 X X Qn Qn J K Qn+1
1 0 0 Qn 0 0 0 0
1 0 1 0 0 0 1 0
1 1 0 1 0 1 0 1
1 1 1 Q’n 0 1 1 1

T.T for J-K Flip-Flop 1 0 0 1

1 0 1 0
Qn Qn+1 J K 1 1 0 1
0 0 0 x 1 1 1 0
0 1 1 x
Characteristics Table for J-K Flip-Flop
1 0 x 1
1 1 x 0

Excitation table for J-K Flip-Flop

 Master - Slave JK Flip Flop
Combination of 2 JK flip-flops in series.
One acts as ‘master’ and the other as ‘slave’
It also includes an Inverter(Not Gate).
Master Slave JK Flip Flop
 Master Slave JK Flip Flop
When the clock is high, master is operational but
slave is not operational(it will keep memory)
When the clock is low, master is not functional
but slave is. The output at slave is fed back to
master but the clock is low. So, In this case effect of
feedback is eliminated(which eliminates racing)
CLK J K Qn+1
0 X X Qn
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Q’n

T.T for J-K Flip-Flop

 Conversion of Flip-Flop
(Realization of one Flip-Flop using other Flip-Flop)
Steps for Flip-Flop Conversion
Make Characteristics table for required flip-flop.
Make Excitation table for available flip-flop.
Write Boolean expression for available flip-flop.
Draw the Block Diagram.
Example 1 – JK to D
Required flip-flop : D, Available flip-flop : JK
Qn D Qn+1 J K Qn Qn+1 J K
0 0 0 0 x 0 0 0 x
0 1 1 1 x 0 1 1 x
1 0 0 x 1 1 0 x 1
1 1 1 x 0 1 1 x 0

Excitation table of JK ( available f/f))

Char table of D ( required f/f))

D J Qn
Using K map
J=D Clk
K = D’
D’ K Q’n
Example 2 – SR to JK
Required flip-flop : JK, Available flip-flop : SR
Qn J K Qn+1 S R Qn Qn+1 S R
0 0 0 x
0 0 0 0 o x 0 1 1 0
0 0 1 0 0 x 1 0 0 1
0 1 0 1 1 0 1 1 x 0
0 1 1 1 1 0
1 0 0 1 x 0
1 0 1 0 0 1
1 1 0 1 x 0
1 1 1 0 0 1

From K map
S = Qn’J R = Q nK
Example 3 – T to D
Required flip-flop : T Available flip-flop : D
 Direct Inputs
Also called asynchronous inputs.
Flip-flop have control over the outputs (Q and Q’)
regardless of clock signal.
These inputs are called the preset (PRE) and clear
(CLR).
When preset = 0, Q equals to 1
When clear = 0, Q equals to 0
 State Diagram and State Table

x/y
P.S N.S

Qn x=input Qn+1
y=output

The relationship that exists among the inputs, outputs,

present states and next states can be specified by either the
State Diagram or State Table.
Design Procedure for Sequential Circuit
Obtain the state table.
Reduce the no. of state using state reduction
method(If possible)
Do state assignment(If required)
Determine the number of flip flop required.
Derive circuit excitation table from state
table/diagram.
Obtain the expression for circuit output and flip flop
output.
Implement the circuit.
State Reduction and Assignment
Present State Next State Output
x=0 x=1 x=0 X=1
A B C 1 0
B F D 0 0
C D E 1 1
D F E 0 1
E A D 0 0
F B C 1 0

Present State Next State Output

x=0 x=1 x=0 X=1
A B C 1 0
B A D 0 0
C D E 1 1
D A E 0 1
E A D 0 0
Present State Next State Output
x=0 x=1 x=0 X=1
A B C 1 0
B A D 0 0
C D B 1 1
D A B 0 1

A 00
0/
0

0/
0
0/

1/

0
1

0/
1/

1
1/1
0/0 C B 1/1
0/0 10 01
0
1/
0/

0
1

1/

0/
D

1
1/1 11 1/1
Design a sequential circuit from the following state diagram using T flip-flop.
0/0
00

1/
1/

1
1/0 0/1
01 10

0
0/
0/
0
11
1/0

Present State Next State Output

x=0 x=1 x=0 X=1
0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 0 1 0 0 0 1 1
1 1 1 0 1 1 0 0
 0/0
00

1/
1/

1
1/0 0/1
01 10

0
0/

0/
0
11
1/0
Present State Next State Output Using T f/f
(y)
Qa Qb x Qa + Qb+ Ta Tb
Ta = Qa’.Qb.x’ +Qa.Qb’x

0 0 0 0 0 0 0 0 Tb = Qa’.Qb’.x + Qa.Qb.x’
0 0 1 0 1 0 0 1 Y = Qa.Qb’.x’ + Qa. Qb’ .
0 1 0 1 1 0 1 0 x
= Qa.Qb’(x+x’)
0 1 1 0 1 0 0 0 = Qa.Qb’

1 0 0 1 0 1 0 0
1 0 1 0 0 1 1 0
1 1 0 1 0 0 0 1
1 1 1 1 1 0 0 0
Ta = Qa’.Qb.x’ +Qa.Qb’x

Tb = Qa’.Qb’.x + Qa.Qb.x’

Y = Qa.Qb’.x’ + Qa. Qb’ .

x
= Qa.Qb’(x+x’)
= Qa.Qb’
From the state diagram given below, Design a Sequential circuit using
SR flip-flop.
0/0
00

0
1/

1/
1

Present State Next State Outp Using SR f/f

01 10 ut
0/0 (y)
Qa Qb x Qa + Qb+ Sa Ra Sb Rb
0
0/
0/
0

11
1/0 0 0 0 0 0 0 o x 0 x
0 0 1 0 1 0 0 x 1 0
0 1 0 1 1 0 1 0 x 0
0 1 1 0 1 0 0 x x 0
1 0 0 1 0 0 x 0 0 x
1 0 1 0 0 1 0 1 x x
1 1 0 1 0 0 x o 0 1
 Present State Next State Output Using SR f/f
(y)
Qa Qb x Qa + Qb+ Sa Ra Sb Rb

0 0 0 0 0 0 o x 0 x
0 0 1 0 1 0 0 x 1 0
0 1 0 1 1 0 1 0 x 0
0 1 1 0 1 0 0 x x 0
1 0 0 1 0 0 x 0 0 x
1 0 1 0 0 1 0 1 o x
1 1 0 1 0 0 x o 0 1
1 1 1 1 1 0 x 0 x 0

Sa(Qa,Qb,x) = Σ (2) & d(Qa,Qb,x) = Σ (4,6,7)

Ra(Qa,Qb,x) = Σ (5) & d(Qa,Qb,x) = Σ (0,1,3)
Sb(Qa,Qb,x) = Σ (1) & d(Qa,Qb,x) = Σ (2,3,7)
Rb(Qa,Qb,x) = Σ (6) & d(Qa,Qb,x) = Σ (0,4,5)
y(Q ,Q ,x) = Σ (5)
Sa(Qa,Qb,x) = Σ (2) & d(Qa,Qb,x) = Σ (4,6,7) Sb(Qa,Qb,x) = Σ (1) & d(Qa,Qb,x) = Σ (2,3,7)

Sa = Qbx' Sb = Q'ax

Ra(Qa,Qb,x) = Σ (5) & d(Qa,Qb,x) = Σ (0,1,3) Rb(Qa,Qb,x) = Σ (6) & d(Qa,Qb,x) = Σ (0,4,5)

Ra = Q'bx Rb = Qax'
y(Qa,Qb,x) = Σ (5)

y = QaQ'bx

y = QaQ'bx
Sa = Qbx'
Sb = Q'ax
Ra = Q'bx
Rb = Qax'
y = QaQ'bx Sa = Qbx' Sb = Q'ax Ra = Q'bx Rb = Qax'
Design a sequential circuit from the following state diagram using S-R flip-flop.
0/1
00

1/
1/

0
1/1 0/0
01 10

0
1/
0/
1
11
0/1