Microcontrollers vs

Microprocessors
Louis WY Liu
Room 319
Building 3
Vietnamese German University
Microprocessors
Microprocessor is a brain of computer.
It is a single chip which is capable of processing data.
It controls all components, including the memory, i/o, and external.
It executes sequence of instructions.
Microprocessors fetch, decode and execute the instructions.
Internal architecture of microprocessors is complex.
Microprocessors consist of
• Registers :– They are temporary storage location for performing
instructions or data.
• Athematic Logic Unit (ALU):- It performs athematic and logic
operations.
• Timing and Control unit:- Keeps all other parts of systems (reg, ALU,
Memory and I/O) working together in the right time sequence.
 Evolution of Intel Microprocessors
• 1939-1954 -> Vacuum tubes
• 1954 – 1959 -> Transistors
• 1959 – 1971 -> IC
• 1971 – present -> Microprocessors
• Microprocessor is scaling from 4004 to Pentium 4.
• Microprocessor is identified with the help of word size of data.
• ALU can perform 4-bit data operation at a time. Then, these type of microprocessors
• 16-bit processors can perform 16 bit operations at a time. Eg. 8086, 8088, zilog2800, 80186, 80286
• 32-bit processors
Intel 90386, 80387, 80486
Intel Pentinum Intel Pentium Pro, Intel Pentium II, Intel Pentium III, Intel Pentium IV, Intel Dual Core
. 64- Bit processors
Intel Core 2,
Intel Core I7,
Intel Core I5,
Intel Core I3.
Microprocessor is externally connected to
• Input: It is used to give the i/p data to the microprocessors
• Output: It is used to provide the result of calculation
• Memory: It is used to store the data
System Architecture of Microprocessor
Overview of Microcontrollers
Microcontrollers integrate microprocessor, I/O ports and memory into a
single chip.
Our personal computers are general-purpose computers, while
microcontrollers are tailored to take inout from the physical world and
control output devices in the physical world.
Another difference between our computers and the microcontrollers is:
• Microcontrollers require less power than a those other processors, and
they’re easier to interface with the physical world through input circuits
called sensors and output circuits called actuators.
• They can communicate with other processors through various
communication interfaces.
• Examples: IBM RS6000, DEC Alpha 21064, DEC Alpha 21164, etc.
 Microprocessors and Microcontrollers
• Microcontrollers integrate electronic computing device that includes three
major components on a single chip.

• Support devices
- Timers, A/D converters, Serial I/O,
•
System Architecture of a Typical
Microcontroller
• Bus is the communication line
 Microprocessor vs AVR Microcontroller
Microprocessor Microcontroller
CPU is stand-alone, but RAM, ROM, I/O, timer are separate CPU, RAM, ROM I/O are all integrated on a single chip
and externally connected
Designer can decide on the amount of ROM, RAM and I/O Fixed amount of ROM, RAM, I/O Ports
ports
Expensive Suitable for applications in which costs, power, and space
are critical.
General Purpose (It can be used as the heart of a computer, Specific in terms of Purpose
or a core of a vector network analyzer)
High processing power Low processing power

Doesn’t support bit addressability Bit-level addressability

Instruction sets focus on processing intensive operations Instruction sets focus on control and bit level operations

32/64 bit Typically 8/16 bit

Typically, deep pipelining (5-20 stages) Typically, single-cycle pipeline
Based on Complex Instruction Set Computer (CISC) Based on Reduced Instruction Set Computer (RISC)
architecture architecture
Based on von Neumann architecture Based on Harvard architecture
Bit Addressability in AVR Microcontrollers
Thus, bit-addressable means you can independently manipulate individual bits from
a memory (RAM, register or likewise) without disturbing the others.
Bit addressing isn’t common in microprocessor, which is typically 32-bit or more, but
if you need to do it then you would probably go for extending the ISA with RISC-V
these days.
In AVR microcontrollers, bit-addressability allows you to manipulate individual bits
within a port, giving you more control over the specific pins you want to set or clear.
The AVR microcontroller has four 8-bit I/O ports named PORTA, PORTB, PORTC and
PORTD, which are all general purpose. For example:

SBI PORTA b0 //set bit of portA

CBI PORTA b0 // clear bit of portA
 CISC and RISC
• The simplest way to explain the difference between CISC and RISC is to use the digital multiplication process as an example.
The process of multiplication involves steps that multiplies two numbers in memory.
• In CISC approach, the objective is to complete a task in as few lines of assembly as possible. To achieve this objective, we will
most likely build hardware capable of understanding and executing a series of operations. At the end, we might end up with
an instruction called "MULT". When executed, this instruction loads the two values into separate registers, say A and B,
multiplies the operands in the execution unit, and then stores the product in the appropriate register:
MULT A, B.
Here, MULT is a complex instruction that does not require the programmer to explicitly call any loading or storing
functions. It closely resembles a command in a higher level language.
• In RISC approach, RISC processors only use simple instructions that can be executed within one or two clock cycles. In AVR
processors, the "MULT" command as described above must be realized in multiple separate commands: "LDR," which moves
data from the memory bank to a register, "MUL," which finds the product of two operands located within the registers, and
"ST," which moves data from a register to the memory banks. In order to perform the exact series of steps described in the
CISC approach, a programmer would need to code four lines of assembly:
.def ResL = R0
.def ResM = R1
.def m1 = R16
.def m2 = R17
ldi m1, 250
ldi m2, 100
mul m1, m2
 RISC and CSIS
Earlier when programming was done using assembly language, a need was felt to make instruction do more tasks because
programming in assembly was tedious and error-prone due to which CISC architecture evolved but with the uprise of high-
level language dependency on assembly reduced RISC architecture prevailed.

Reduced Instruction Set Architecture (RISC) –

The main idea behind this is to make hardware simpler by using an instruction set composed of a few basic steps for loading,
evaluating, and storing operations just like a load command will load data, a store command will store the data.
Characteristics of RSIC includes:
• Simpler instruction, hence simple instruction decoding.
• Instruction comes undersize of one word.
• In microcontroller, CPU Time is reduced by reducing the number of cycles per instructions. In AVR microcontrollers, for
example, most instructions take a single clock cycle to get executed.
• More general-purpose registers.
• Simple Addressing Modes.
• Fewer Data types.
• A pipeline can be achieved.
Von Neumann Architecture Vs Harvard Architecture
Von Neumann architecture:
• Instructions and data both are stored in the same memory. So same buses are used to fetch instructions and data.
This means the CPU cannot do both things together (read the instruction and read/write data).
• In a system with a pure von Neumann architecture, instructions and data are stored in the same memory, so
instructions are fetched over the same data path used to fetch data. This means that a CPU cannot simultaneously
read an instruction and read or write data from or to the memory.
Harvard Architecture:
• In Harvard architecture, it contains separate storage and separate buses (signal path) for instruction and data. It
was basically developed to overcome the bottleneck of Von Neumann Architecture. The main advantage of having
separate buses for instruction and data is that the CPU can access instructions and read/write data at the same
time.
• In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory
access at the same time, even without a cache. A Harvard architecture computer can thus be faster for a given
circuit complexity because instruction fetches and data access do not contend for a single memory pathway.
• Also, a Harvard architecture machine has distinct code and data address spaces: instruction address zero is not
the same as data address zero. Instruction address zero might identify a twenty-four-bit value, while data address
zero might indicate an eight-bit byte that is not part of that twenty-four-bit value.
Block
diagram of
Harvard
Architecture:
Modern uses of the Harvard architecture
• Digital signal processors (DSPs) generally execute small, highly optimized audio or
video processing algorithms. They avoid caches because their behavior must be
extremely reproducible. The difficulties of coping with multiple address spaces are of
secondary concern to speed of execution. Consequently, some DSPs feature multiple
data memories in distinct address spaces to
facilitate SIMD and VLIW processing. Texas Instruments TMS320 C55x processors, for
one example, feature multiple parallel data buses (two write, three read) and one
instruction bus.
• Microcontrollers are characterized by having small amounts of program (flash
memory) and data (SRAM) memory, and take advantage of the Harvard architecture
to speed processing by processing instructions and data at the same time. The
separate storage means the program and data memories may feature different bit
widths, for example using 16-bit-wide instructions and 8-bit-wide data. They also
mean that instruction prefetch can be performed in parallel with other activities.
Examples include the Microchip’s PIC and AVR.
RISC and CISC (Con’t)
Complex Instruction Set Architecture (CISC) –

The main idea is that a single instruction will do all loading, evaluating, and
storing operations just like a multiplication command will do stuff like loading
data, evaluating, and storing it, hence it’s complex.
Both approaches try to increase the CPU performance
RISC: Reduce the cycles per instruction at the cost of the number of
instructions per program.

CISC: The CISC approach attempts to minimize the number of instructions per
program but at the cost of an increase in the number of cycles per instruction.
RISC and CISC (Con’t)
Both approaches try to increase the CPU performance

RISC: Reduce the cycles per instruction at the cost of the number of
instructions per program.

CISC: The CISC approach attempts to minimize the number of

instructions per program but at the cost of an increase in the number
of cycles per instruction.
Other state-of-art architecture: EPIC (Explicitly Parallel Instruction Computing)

• In this class of processor, instructions are computed parallelly with the

help of compilers.
• The goal is to process the complex instructions in fewer clock
frequencies.
• The instructions are encoded in 128-bit bundles. Where each bundle
contains three instructions encoded in 41 bits each and a 5-bit
template. This 5-bit template contains information about the type of
instructions and that which instructions can be executed in parallel.
• Examples are IA-64 (Intel Architecture-64), etc.