Department of ECE

ASIC & FPGA CHIP DESIGN

21EC3063
Topic:

COMBINATIONAL LOGIC PLDS

Session - 1

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 AIM OF THE SESSION

To familiarize students with the basic concept of Programmable Logic Devices

INSTRUCTIONAL OBJECTIVES

This Session is designed to: Describe PLDs

LEARNING OUTCOMES

At the end of this session, you should be able to: Define the PLDs

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 SESSION INTRODUCTION

Programmable Logic Devices (PLD)

Programmable logic falls into two different types:

1. Devices that can be programmed only once.
 Factory Programmable
2. Devices that can be reprogrammed multiple times.
 Field programmable

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 PROGRAMMABLE LOGIC DEVICES (PLD)

Problems by Using Basic Gates

 Many components on PCB: As no. of components rise, nodes interconnection complexity grow
exponentially.

 Growth in interconnection will cause increase in interference, PCB size, PCB design cost, and
manufacturing time.

Purpose of PLD’s:

 The purpose of a PLD device is to permit elaborate digital logic designs to be implemented by
the user in a single device.

 Can be erased electrically and reprogrammed with a new design, making them very well suited
for academic and prototyping.

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 SESSION DESCRIPTION

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 Classification of PLDs

PROM
Simple PLD
PLA

Programmable
Complex PLD PAL
Logic Device

FPGA

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 SIMPLE PROGRAMMABLE LOGIC DEVICES (SPLD)

 Simple Programmable Logic Devices (SPLDs) are the integrated circuits.

 They contain an array of AND gates & another array of OR gates.

 There are three kinds of SPLDs based on the type of arrays, which has
programmable feature.
1.Programmable Read Only Memory (PROM)
2. Programmable Array Logic (PAL)
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 SIMPLE PROGRAMMABLE LOGIC DEVICES
(SPLD)

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 PROGRAMMABLE READ ONLY MEMORY (PROM)

1. Programmable Read Only Memory (PROM)

 Read Only Memory (ROM) is a memory device, which stores the binary
information permanently.

 If the ROM has programmable feature, then it is called as Programmable

ROM (PROM).

 PROM is a programmable logic device that has fixed AND array & Programmable
OR array.

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 Programmable Symbology

10
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 Programmable Read Only Memory (PROM)
Problem: Implement the following Boolean functions using PROM.
A(X,Y,Z)=∑m(5,6,7)
B(X,Y,Z)=∑m(3,5,6,7)
Solution: The given two functions are in sum of min terms form and each function is
having three variables X, Y & Z. So, we require a 3 to 8 decoder and two
programmable OR gates for producing these two functions.

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 Implement Full Adder by using PROM
• PROM Implementation
SUM= FULL ADDER LOGIC
CARRY=

0
1
A 2
B 3×8 3
Decoder 4
C
5
6
7

SUM CARRY
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 Try on Your Own…!
Problem: Implement 1-bit Comparator Circuit using PROM

Hints:
1. Write the Truth Table of 1-bit Comparator
2. Write the Minterms of A=B, A<B & A>B, from the Truth Table
3. Take Appropriate Decoder and Proceed with the Connections

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 PROGRAMMABLE ARRAY LOGIC (PAL)
 PAL is a programmable logic device that has Programmable AND array & fixed OR
array.

 The advantage of PAL is that we can generate only the required product terms of
Boolean function instead of generating all the min terms by using programmable
AND gates.

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 Problem: Implement the following Boolean functions using PAL.
A=XY+XZ′A=XY+XZ′
B=XY′+YZ′
Solution: The given two functions are in sum of products form. There are two product
terms present in each Boolean function. So, we require four programmable AND
gates & two fixed OR gates for producing those two functions.

X Y Z

XY

A
XZ’

XY’

B
YZ’

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 Implement Full Adder by using PAL
• PAL Implementation
SUM = .C + + .B. + .B.C
Carry = AB + BC + AC
PAL Table

AND Inputs
Min Term Outputs
A B C
0 0 1
1 0 0
0 1 0
1 1 1
AB 1 1 -
BC - 1 1 Carry = AB + BC
+ AC
AC 1 - 1

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 Implementation of Full Adder using PAL

SUM = .C + + .B. + .B.C

Carry = AB + BC + AC
A B C

SUM

CARRY

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 Try this…!
Problem: Implement the following Boolean functions using PAL

A(X,Y,Z) = Sum of Even Numbers (include Zero also)

B(X,Y,Z) = Sum of Odd Numbers

04/17/2024 Source: Confidential 18

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 Try on Your Own…!
Problem: Implement the following Boolean functions using PAL

A(X,Y,Z) = X’YZ + XY’Z + XYZ’

B(X,Y,Z) = Y’Z’ + XYZ

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 PROGRAMMABLE LOGIC ARRAY (PLA)

 PLA is a programmable logic device that has both Programmable AND array &
Programmable OR array. Hence, it is the most flexible PLD.

 Advantage of PLA is Design checking is easy, and design change is also easy

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 Problem: Implement the following Boolean functions using PLA.
X = AB + AC’
Y = AB’ +BC‘ + AC’
Solution:The above given two Boolean functions are in the form of SOP (sum of
products). The product terms present in the Boolean expressions are X & Y, and one
product term that is AC’ is common in every equation. So, the total required logic gates
for generating the above two equations is AND gates-4, OR programmable OR gates-2.

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 Full Adder using PLA
• PLA Implementation
SUM = .C + + .B. + .B.C
Carry = AB + BC + AC

PLA Table
AND Inputs OR Outputs
Min
Term A B C SUM CARR
Y
.C 0 0 1 1 -
1 0 0 1 -
.B. 0 1 0 1 -
.B.C 1 1 1 1 -
AB 1 1 - - 1
BC - 1 1 - 1
AC 1 - 1 - 1
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 Implementation of Full Adder using PLA

A B C SUM = .C + + .B. + .B.C

Carry = AB + BC + AC

SUM CARRY
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 Try this…!
Problem: Implement the following Boolean functions using PLA

A(X,Y,Z) = Σm(1,2,3,6)
B(X,Y,Z) = Σm(0,1,4,5,7)

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 Try this on Your Own…!
Problem: Implement 2-bit Binary to Gray Code Convertor Circuit using PLA

Hints:
1. Write the Truth Table for 2-bit Binary to Gray Code Convertor.
2. Write the Corresponding Expressions of the Minterms, for the Obtained
Gray Code Outputs.
3. Proceed with PLA Implementation.

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 SESSION DESCRIPTION (Cont..)

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 EXAMPLES

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 SUMMARY

• Programmable Logic Devices (PLDs) come in two general

categories. The categories are Simple Programmable Logic Devices
(SPLDs) and High-Density Programmable Logic Devices
(HDPLDs).
• HDPLDs come in two architectures, which are Complex
Programmable Logic Devices (CPLDs) and Field Programmable
Gate Arrays (FPGAs).
• Both CPLDs and FPGAs are available in SRAM based
programming configuration but only CPLDs can be EPROM or
EEPROM programmed.

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 SELF-ASSESSMENT QUESTIONS

1. Which type of PLD should be used to program basic logic functions

(a) PLA
(b) PAL
(c) CPLD
(d) SLD

2. The content of a simple programmable logic device (PLD) consists of:

(a) fuse-link arrays

(b) thousands of basic logic gates
(c) advanced sequential logic functions
(d) . thousands of basic logic gates and advanced sequential logic functions
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 TERMINAL QUESTIONS

1. Illustrate various PLD and its classification

2. List the digital circuit implementation platforms

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 REFERENCES FOR FURTHER LEARNING OF THE SESSION

Reference Books:
1. Bob Zeidman, “Designing with FPGAs and CPLDs”, CMP Books, ISBN: 1-57820-112-8.
2. Stephen Brown and Zvonko Vranesic “Fundamentals of Digital Logic with Verilog Design”
McGraw-Hill.
3. Pak K. Chan, Samiha Mourad, “Digital Design Using Field Programmable Gate Array”, Pearson
Education – 2009

Sites and Web links:

1. https://youtu.be/gCAYY0fHPq4

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 THANK YOU

Team – ASIC & FPGA Chip Design

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