║JAI SRI GURUDEV║

Sri AdichunchanagiriShikshana Trust (R)

SJB INSTITUTE OF TECHNOLOGY

BGS Health & Education City, Kengeri , Bangalore – 60 .

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

CO & ARM Microcontrollers

[21EC52]

Module-2
Memory System & Basic Processing Unit

Dr. Supreeth H S G
Associate Professor
Dept. of ECE SJBIT
1
 VTU syllabus
Module – 02

Memory System: Basic Concepts, Semiconductor RAM Memories, Read Only Memories, Speed,
Size, and Cost, Cache Memories – Mapping Functions, Replacement Algorithms, Performance
Considerations.
Textbook 1: Chapter 5 – 5.1 to 5.4, 5.5 (5.5.1, 5.5.2), 5.6

Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete Instruction,

Multiple Bus Organization, Hard-wired Control, Micro programmed Control. Basic concepts of
pipelining,
Textbook 1: Chapter7, Chapter 8 – 8.1

Textbook:

Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer Organization, 5th Edition, Tata McGraw
Hill, 2002. (Listed topics only from Chapters 1, 2, 4, 5, 8).
 Contents
1. Basic Concepts
2. Semiconductor RAM Memories
3. Read Only Memories
4. Speed, Size and Cost
5. Cache Memories –
Mapping Functions
Replacement Algorithms
6. Performance Considerations.
3
 1.Some basic concepts
• Maximum size of the Main Memory
• byte-addressable
• CPU-Main Memory Connection
Processor Memory
k-bit
address bus
MAR
n-bit
data bus Up to 2 k addressable
MDR locations

Word length = n bits

Control lines
( R / W, MFC, etc.)
 Some basic concepts(Contd.,)
Measures for the speed of a memory:
 memory access time.
 memory cycle time.
An important design issue is to provide a
computer system with as large and fast a
memory as possible, within a given cost target.
Several techniques to increase the effective size
and speed of the memory:
 Cache memory (to increase the effective speed).
 Virtual memory (to increase the effective size).
2. Semiconductor RAM memories
The Memory System
 Internal organization of memory chips
• Each memory cell can hold one bit of information.
• Memory cells are organized in the form of an array.
• One row is one memory word.
• All cells of a row are connected to a common line, known as the
“word line”.
• Word line is connected to the address decoder.
• Sense/write circuits are connected to the data input/output lines of
the memory chip.
Internal organization of memory chips
(Contd.,)
7 7 1 1 0 0
W0

•
•
•
FF FF
A0 W1

•
•
•
A1
Address Memory
• • • • • • cells
decoder • • • • • •
A2 • • • • • •

A3

W15
•
•
•

Sense / Write Sense / Write Sense / Write R /W

circuit circuit circuit
CS

Data input /output lines: b7 b1 b0

 SRAM Cell
• Two transistor inverters are cross connected to implement a basic flip-flop.
• The cell is connected to one word line and two bits lines by transistors T1 and T2
• When word line is at ground level, the transistors are turned off and the latch
retains its state
• Read operation: In order to read state of SRAM cell, the word line is activated to
close switches T1 and T2. Sense/Write circuits at the bottom monitor the state of b
and b’
b b¢

T1 T2
X Y

Word line
Bit lines
 Asynchronous DRAMs
• Static RAMs (SRAMs):
– Consist of circuits that are capable of retaining their state as long as the power
is applied.
– Volatile memories, because their contents are lost when power is interrupted.
– Access times of static RAMs are in the range of few nanoseconds.
– However, the cost is usually high.

• Dynamic RAMs (DRAMs):

– Do not retain their state indefinitely.
– Contents must be periodically refreshed.
– Contents may be refreshed while accessing them for reading.
 Asynchronous DRAMs
• Each row can store 512 bytes.
RAS 12 bits to select a row, and 9
bits to select a group in a row.
Row
Total of 21 bits.
address Row 4096´ ( 512´ 8)
latch decoder cell array • First apply the row address,
RAS signal latches the row
address. Then apply the
column address, CAS signal
A20 - 9 ¤ A8 - 0 Sense / Write CS latches the address.
circuits
•R /WTiming of the memory unit is
controlled by a specialized unit
Column which generates RAS and CAS.
address Column
decoder • This is asynchronous DRAM
latch

CAS D7 D0
 Fast Page Mode
 Suppose if we want to access the consecutive bytes in the
selected row.
 This can be done without having to reselect the row.
 Add a latch at the output of the sense circuits in each row.
 All the latches are loaded when the row is selected.
 Different column addresses can be applied to select and place different bytes on the
data lines.
 Consecutive sequence of column addresses can be applied
under the control signal CAS, without reselecting the row.
 Allows a block of data to be transferred at a much faster rate than random accesses.
 A small collection/group of bytes is usually referred to as a block.
 This transfer capability is referred to as the
fast page mode feature.
 Synchronous DRAMs
•Operation is directly synchronized
Refresh
counter with processor clock signal.
•The outputs of the sense circuits are
connected to a latch.
Row
•During a Read operation, the
Row
address decoder Cell array contents of the cells in a row are
latch
Row/Column loaded onto the latches.
address •During a refresh operation, the
Column Column Read/Write contents of the cells are refreshed
address
counter decoder circuits & latches without changing the contents of
the latches.
•Data held in the latches correspond
Clock
to the selected columns are transferred
R AS to the output.
Mode register
CAS and Data input Data output •For a burst mode of operation,
register register
R/ W timing control successive columns are selected using
CS column address counter and clock.
CAS signal need not be generated
externally. A new data is placed during
Data
raising edge of the clock
 Latency, Bandwidth, and DDRS DRAMs
• Memory latency is the time it takes to transfer
a word of data to or from memory
• Memory bandwidth is the number of bits or
bytes that can be transferred in one second.
• DDRSDRAMs
– Cell array is organized in two banks
 Static memories
21-bit
addresses 19-bit internal chip address Implement a memory unit of 2M
A0
A1 words of 32 bits each.
Use 512x8 static memory chips.
A19 Each column consists of 4 chips.
A20
Each chip implements one byte
position.
A chip is selected by setting its
chip select control line to 1.
Selected chip places its data on the
2-bit
decoder data output line, outputs of other
chips are in high impedance state.
21 bits to address a 32-bit word.
High order 2 bits are needed to
512K ´ 8
memory chip select the row, by activating the
D31-24 D23-16 D 15-8 D7-0
four Chip Select signals.
512K ´ 8 memory chip
19 bits are used to access specific
byte locations inside the selected
19-bit
address
8-bit data
input/output chip.

Chip select
 Dynamic memories
 Large dynamic memory systems can be implemented using
DRAM chips in a similar way to static memory systems.
 Placing large memory systems directly on the motherboard
will occupy a large amount of space.
 Also, this arrangement is inflexible since the memory system cannot be expanded easily.

 Packaging considerations have led to the development of

larger memory units known as SIMMs (Single In-line
Memory Modules) and DIMMs (Dual In-line Memory
Modules).
 Memory modules are an assembly of memory chips on a
small board that plugs vertically onto a single socket on the
motherboard.
 Occupy less space on the motherboard.
 Allows for easy expansion by replacement .
 Memory controller
 Recall that in a dynamic memory chip, to reduce the
number of pins, multiplexed addresses are used.
 Address is divided into two parts:
 High-order address bits select a row in the array.
 They are provided first, and latched using RAS signal.
 Low-order address bits select a column in the row.
 They are provided later, and latched using CAS signal.
 However, a processor issues all address bits at the same
time.
 In order to achieve the multiplexing, memory
controller circuit is inserted between the processor
and memory.
 Memory controller (contd..)
Row/Column
Address address

RAS
R/ W
CAS
Memory
Request controller R/ W
Processor Memory
CS
Clock
Clock

Data

18
 3. Read-Only Memories (ROMs)

The Memory System

 Read-Only Memories (ROMs)
 SRAM and SDRAM chips are volatile:
 Lose the contents when the power is turned off.
 Many applications need memory devices to retain contents after
the power is turned off.
 For example, computer is turned on, the operating system must be
loaded from the disk into the memory.
 Store instructions which would load the OS from the disk.
 Need to store these instructions so that they will not be lost after the
power is turned off.
 We need to store the instructions into a non-volatile memory.
 Non-volatile memory is read in the same manner as volatile
memory.
 Separate writing process is needed to place information in this memory.
 Normal operation involves only reading of data, this type
of memory is called Read-Only memory (ROM).
Read-Only Memories (ROMs)
• Possible configuration of ROM cell .
• A logic value 0 is stored if transistor is
connected to ground at point P. otherwise, a 1 is
stored.
• The bit line is connected through a resistor to
power supply.
• To read the state of the cell word line must be
activated.
• Thus, transistor switch is closed and the voltage
on bit line drops to zero.
• If there is no connection to ground , the bit line
remains at high voltage. Indicating 1.
• A sense circuit at end of bit line generates the
proper output value.
• Data are written into ROM when manufactured.
 Read-Only Memories (Contd.,)
 Read-Only Memory:
 Data are written into a ROM when it is manufactured.
 Programmable Read-Only Memory (PROM):
 Allow the data to be loaded by a user.
 Process of inserting the data is irreversible.
 Storing information specific to a user in a ROM is expensive.
 Providing programming capability to a user may be better.

 Erasable Programmable Read-Only Memory

(EPROM):
 Stored data to be erased and new data to be loaded.
 Flexibility, useful during the development phase of digital systems.
 Erasable, reprogrammable ROM.
 Erasure requires exposing the ROM to UV light.
 Read-Only Memories (Contd.,)
 Electrically Erasable Programmable Read-Only Memory
(EEPROM):
 To erase the contents of EPROMs, they have to be exposed to ultraviolet light.
 Physically removed from the circuit.
 EEPROMs the contents can be stored and erased electrically.
 Flash memory:
 Has similar approach to EEPROM.
 Read the contents of a single cell, but write the contents of an entire
block of cells.
 Flash devices have greater density.
▪ Higher capacity and low storage cost per bit.

 Power consumption of flash memory is very low, making it attractive for

use in equipment that is battery-driven.
 Single flash chips are not sufficiently large, so
larger memory modules are implemented using
flash cards and flash drives.
 4. Memory Hierarchy
Processor •Fastest access is to the data held in
processor registers. Registers are at
Registers the top of the memory hierarchy.
•
Increasing Increasing Increasing Relatively small amount of memory that
size speed cost per bit can be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache. Level 1 (L1) cache
is on the processor chip. Level 2 (L2)
cache is in between main memory and
Secondary L2 processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexepensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk
that will be used in the near future as
secondary close to the processor as possible.
memory
 5. Cache Memories

The Memory System

 Cache Memories
 Processor is much faster than the main memory.
 As a result, the processor has to spend much of its time waiting while instructions and
data are being fetched from the main memory.
 Major obstacle towards achieving good performance.

 Speed of the main memory cannot be increased

beyond a certain point.
 Cache memory is an architectural arrangement
which makes the main memory appear faster to the
processor than it really is.
 Cache memory is based on the property of
computer programs known as “locality of reference”.
 Locality of Reference
 Analysis of programs indicates that many instructions
in localized areas of a program are executed
repeatedly during some period of time, while the
others are accessed relatively less frequently.
 These instructions may be the ones in a loop, nested loop or few procedures calling each
other repeatedly.
 This is called “locality of reference”.
 Temporal locality of reference:
 Recently executed instruction is likely to be executed again very soon.
 Spatial locality of reference:
 Instructions with addresses close to a recently instruction are likely
to be executed soon.
 Cache memories

Main
Processor Cache memory

• Processor issues a Read request, a block of words is transferred from the main
memory to the cache, one word at a time.
• Subsequent references to the data in this block of words are found in the cache.
• At any given time, only some blocks in the main memory are held in the cache.
Which blocks in the main memory are in the cache is determined by a
“mapping function”.
• When the cache is full, and a block of words needs to be transferred
from the main memory, some block of words in the cache must be
replaced. This is determined by a “replacement algorithm”.
 Cache hit
• Existence of a cache is transparent to the processor. The processor issues
Read and
Write requests in the same manner.

• If the data is in the cache it is called a Read or Write hit.

• Read hit:
 The data is obtained from the cache.

• Write hit:
 Cache has a replica of the contents of the main memory.
 Contents of the cache and the main memory may be updated simultaneously.
This is the write-through protocol.
 Update the contents of the cache, and mark it as updated by setting a bit known
as the dirty bit or modified bit. The contents of the main memory are updated
when this block is replaced. This is write-back or copy-back protocol.
 Cache miss
• If the data is not present in the cache, then a Read miss or Write miss
occurs.

• Read miss:
 Block of words containing this requested word is transferred from the memory.
 After the block is transferred, the desired word is forwarded to the processor.
 The desired word may also be forwarded to the processor as soon as it is
transferred without waiting for the entire block to be transferred. This is called
load-through or early-restart.

• Write-miss:
 Write-through protocol is used, then the contents of the main memory are
updated directly.
 If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired word
is overwritten with new information.
 Cache Coherence Problem
• A bit called as “valid bit” is provided for each block.
• If the block contains valid data, then the bit is set to 1, else it is 0.
• Valid bits are set to 0, when the power is just turned on.
• When a block is loaded into the cache for the first time, the valid bit is set to 1.

• Data transfers between main memory and disk occur directly bypassing the cache.
• When the data on a disk changes, the main memory block is also updated.
• However, if the data is also resident in the cache, then the valid bit is set to 0.

• What happens if the data in the disk and main memory changes and the write-
back protocol is being used?
• In this case, the data in the cache may also have changed and is indicated by the
dirty bit.
• The copies of the data in the cache, and the main memory are different. This is
called the cache coherence problem.
• One option is to force a write-back before the main memory is updated from the
disk.
 Contents-Part B
Basic Processing Unit
1. Some Fundamental Concepts
2. Execution of a Complete Instruction
3. Multiple Bus Organization
4. Hard-wired Control
5. Micro programmed Control
6. Basic concepts of pipelining
 1. Fundamental Concepts
• Processor fetches one instruction at a time and perform
the operation specified.
• Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
• Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
• Instruction Register (IR)
 2. Executing an Instruction
• Fetch the contents of the memory location pointed to by
the PC. The contents of this location are loaded into the
IR (fetch phase).
IR ← [[PC]]
• Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
• Carry out the actions specified by the instruction in the
IR (execution phase).
 Internal
Organization
of the
Processor

Figure: Single
bus organizaton
of the datapath
inside a
processor
 Executing an Instruction
• Transfer a word of data from one processor
register to another or to the ALU.
• Perform an arithmetic or a logic operation and
store the result in a processor register.
• Fetch the contents of a given memory location
and load them into a processor register.
• Store a word of data from a processor register
into a given memory location.
Register Transfers Internal processor
bus
Riin

Ri

Riout

Yin

Constant 4

Select MUX

A B
ALU

Zin

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
 Register Transfers
• All operations and data transfers are controlled by the processor clock.
Bus

D Q
1
Q
Riout

Ri in
Clock

Figure 7.3.7.3.Input
Figure Inputand
andoutput
outputgating
gating for one register
register bit.
bit.
 Performing an Arithmetic or Logic
Operation
• The ALU is a combinational circuit that has no internal
storage.
• ALU gets the two operands from MUX and bus. The
result is temporarily stored in register Z.
• What is the sequence of operations to add the contents
of register R1 to those of R2 and store the result in R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
 Fetching a Word from Memory
• Address into MAR; issue Read operation; data into MDR.
Memory-bus Internal processor
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

Figure 7.4.
Figure 7.4. Connection and control
Connection and controlsignals
signalsfor
forregister
registerMDR.
MDR.
 Fetching a Word from Memory
• The response time of each memory access varies (cache
miss, memory-mapped I/O,…).
• To accommodate this, the processor waits until it
receives an indication that the requested operation has
been completed (Memory-Function-Completed, MFC).
• Move (R1), R2
 MAR ← [R1]
 Start a Read operation on the memory bus
 Wait for the MFC response from the memory
 Load MDR from the memory bus
 R2 ← [MDR]
 Timing Step 1 2 3

Clock

MARin MAR ← [R1]

Assume MAR
is always available Address
on the address lines
of the memory bus. Start a Read operation on the memory bus
Read

MR

MDRinE

Data

Wait for the MFC response from the memory

MFC

MDR out Load MDR from the memory bus

R2 ← [MDR]

Figure 7.5. Timing of a memory Read operation.

 Execution of a Complete Instruction
• Add (R3), R1
• Fetch the instruction
• Fetch the first operand (the contents of the
memory location pointed to by R3)
• Perform the addition
• Load the result into R1
 Architecture Internal processor
bus
Riin

Ri

Riout

Yin

Constant 4

Select MUX

A B
ALU

Zin

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
 Execution of a Complete Instruction
Internal processor
bus

Add (R3), R1 Control signals

PC

Instruction
Step Action Address
decoder and
lines
MAR control logic

1 PC out , MAR in , Read, Select4, Add, Zin Memory

bus

2 Zout , PC in , Yin , WMF C MDR

Data
lines IR
3 MDR out , IR in
4 R3 out , MAR in , Read Y
Constant 4 R0
5 R1 out , Yin , WMF C
6 MDR out , SelectY, Add, Zin Select MUX

7 Zout , R1 in , End Add

A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP
Figure 7.6. Con trol sequence for execution of the instruction Add (R3),R1.
Z

Figure 7.1. Single-bus organization of the datapath inside a processor.

 Execution of Branch Instructions
• A branch instruction replaces the contents of
PC with the branch target address, which is
usually obtained by adding an offset X given in
the branch instruction.
• The offset X is usually the difference between
the branch target address and the address
immediately following the branch instruction.
• Conditional branch
Execution of Branch Instructions

Step Action

1 PCout , MAR in , Read, Select4, Add, Z in

2 Zout , PC in , Yin , WMF C
3 MDR out , IR in
4 Offset-field-of-IRout , Add, Z in
5 Z out , PCin , End

Figure 7.7. Control sequence for an unconditional branch instruction.

3. Multiple-Bus Organization
Bus A Bus B Bus C

Incrementer

PC

Register
file

Constant 4

MUX
A

ALU R

Instruction
decoder

IR

MDR

MAR

Memory bus Address

data lines lines

Figure 7.8. Three-bus organization of the datapath.

 Multiple-Bus Organization
• Add R4, R5, R6

Step Action

1 PCout , R=B, MAR in , Read, IncPC

2 WMFC
3 MDR outB , R=B, IR in
4 R4outA , R5outB , SelectA, Add, R6 in , End

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.
 Quiz
Internal processor
bus
Control signals

• What is the control PC

sequence for
Instruction
Address
decoder and
lines
MAR control logic

execution of the Memory

bus

instruction Data
lines
MDR
IR

Add R1, R2 Constant 4

Y
R0

including the Select MUX

instruction fetch Add

Sub
A B
R n - 1 

phase? (Assume
ALU
control ALU
lines
Carry-in

single bus
XOR TEMP

architecture)
Figure 7.1. Single-bus organization of the datapath inside a processor.
4.Hardwired Control
 Overview
• To execute instructions, the processor must
have some means of generating the control
signals needed in the proper sequence.
• Two categories: hardwired control and
microprogrammed control
• Hardwired system can operate at high speed;
but with little flexibility.
Control Unit Organization
CLK Control step
Clock counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals

Figure 7.10. Control unit organization.

Detailed Block Description
CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 Tn

INS 1
External
INS 2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

 Generating Zin
• Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T4 T6

T1

Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.
 Generating End
• End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…
Branch<0
Add Branch
N N

T7 T5 T4 T5

End

Figure 7.13. Generation of the End control signal.

A Complete Processor
Instruction Integer Floating-point
unit unit unit

Instruction Data
cache cache

Bus interface
Processor

System bus

Main Input/
memory Output

Figure 7.14. Block diagram of a complete processor.

5. Microprogrammed Control
 Overview
• Control signals are generated by a program similar to machine language
programs.
• Control Word (CW); microroutine; microinstruction

MDRout

WMFC
MAR in

Select
PCout
Micro -

R1out

R3out
Read
PCin

R1 in
Add

End
Z out
IRin
Yin
instruction

Zin
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An example of microinstructions for Figure 7.6.

 Overview

Step Action

1 PC out , MAR in , Read, Select4, Add, Zin

2 Zout , PC in , Yin , WMF C
3 MDR out , IR in
4 R3 out , MAR in , Read
5 R1 out , Yin , WMF C
6 MDR out , SelectY, Add, Zin
7 Zout , R1 in , End

Figure 7.6. Con trol sequence for execution of the instruction Add (R3),R1.
 Overview
• Control store
Starting
IR address
generator One function
cannot be carried
out by this simple
organization.

Clock P C

Control
store CW

Figure 7.16. Basic organization of a microprogrammed control unit.

 Overview
• The previous organization cannot handle the situation when the control unit is
required to check the status of the condition codes or external inputs to
choose between alternative courses of action.
• Use conditional branch microinstruction.
Address Microinstruction

0 PCout , MAR in , Read, Select4, Add, Z in

1 Zout , PC in , Yin , WMF C
2 MDR out , IR in
3 Branch to starting addressof appropriate microroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, then branch to microinstruction 0
26 Offset-field-of-IR out , SelectY, Add, Z in
27 Zout , PC in , End

Figure 7.17. Microroutine for the instruction Branch<0.

 Overview
External
inputs

Starting and
branch address Condition
IR codes
generator

Clock m PC

Control
store CW

Figure 7.18. Organization of the control unit to allow

conditional branching in the microprogram.
 Microinstructions
• A straightforward way to structure
microinstructions is to assign one bit position
to each control signal.
• However, this is very inefficient.
• The length can be reduced: most signals are
not needed simultaneously, and many signals
are mutually exclusive.
• All mutually exclusive signals are placed in the
same group in binary coding.
Partial Format for the Microinstructions
Microinstruction

F1 F2 F3 F4 F5

F1 (4 bits) F2 (3 bits) F3 (3 bits) F4 (4 bits) F5 (2 bits)

0000: No transfer 000: No transfer 000: No transfer 0000: Add 00: No action
0001: PCout 001: PCin 001: MARin 0001: Sub 01: Read
0010: MDRout 010: IRin 010: MDRin 10: Write
0011: Zout 011: Z in 011: TEMP in
0100: R0out 100: R0in 100: Y in 1111: XOR
0101: R1out 101: R1in
0110: R2out 110: R2 in 16 ALU
functions
0111: R3 out 111: R3 in
1010: TEMPout
1011: Offset out

F6 F7 F8
What is the price paid for
this scheme?
F6 (1 bit) F7 (1 bit) F8 (1 bit)

0: SelectY 0: No action 0: Continue

1: Select4 1: WMFC 1: End

Figure 7.19. An example of a partial format for field-encoded microinstructions.

 Further Improvement
• Enumerate the patterns of required signals in
all possible microinstructions. Each
meaningful combination of active control
signals can then be assigned a distinct code.
• Vertical organization
• Horizontal organization
 Microprogram Sequencing
• If all microprograms require only straightforward
sequential execution of microinstructions except for
branches, letting a μPC governs the sequencing would be
efficient.
• However, two disadvantages:
 Having a separate microroutine for each machine instruction results in a
large total number of microinstructions and a large control store.
 Longer execution time because it takes more time to carry out the
required branches.
• Example: Add src, Rdst
• Four addressing modes: register, autoincrement,
autodecrement, and indexed (with indirect forms).
- Bit-ORing
- Wide-Branch Addressing
- WMFC
 Mode

Contents of IR OP code 0 1 0 Rsrc Rdst

11 10 8 7 4 3 0

Address Microinstruction
(octal)

000 PCout, MARin , Read, Select4 , Add, Zin

001 Zout , PCin, Yin, WMFC
002 MDRout, IRin
003 m Branch {m PC ¬ 101 (from Instruction decoder);
m PC5,4 ¬ [IR10,9]; m PC3 ¬ [IR 10] × [IR9] × [IR8]}
121 Rsrcout , MARin , Read, Select4, Add, Zin
122 Zout , Rsrcin
123 mBranch {mPC ¬ 170;mPC0 ¬ [IR8]}, WMFC
170 MDRout, MARin , Read, WMFC
171 MDRout, Yin
172 Rdstout , SelectY, Add, Zin
173 Zout , Rdstin , End

Figure 7.21. Microinstruction for Add (Rsrc)+,Rdst.

Note: Microinstruction at location 170 is not executed for this addressing mode.
Microinstructions with Next-Address Field
• The microprogram we discussed requires several branch
microinstructions, which perform no useful operation in
the datapath.
• A powerful alternative approach is to include an address
field as a part of every microinstruction to indicate the
location of the next microinstruction to be fetched.
• Pros: separate branch microinstructions are virtually
eliminated; few limitations in assigning addresses to
microinstructions.
• Cons: additional bits for the address field (around 1/6)
Microinstructions with Next-Address Field
IR

External Condition
Inputs codes

Decoding circuits

AR

Control store

Next address I R

Microinstruction decoder

Control signals

Figure 7.22. Microinstruction-sequencing organization.

 Microinstruction

F0 F1 F2 F3

F0 (8 bits) F1 (3 bits) F2 (3 bits) F3 (3 bits)

Address of next 000: No transfer 000: No transfer 000: No transfer

microinstruction 001: PC out 001: PCin 001: MAR in
010: MDR out 010: IRin 010: MDR in
011: Z out 011: Z in 011: TEMP in
100: Rsrc out 100: Rsrc in 100: Y in
101: Rdst out 101: Rdst in
110: TEMP out

F4 F5 F6 F7

F4 (4 bits) F5 (2 bits) F6 (1 bit) F7 (1 bit)

0000: Add 00: No action 0: SelectY 0: No action

0001: Sub 01: Read 1: Select4 1: WMFC
10: Write
1111: XOR

F8 F9 F10

F8 (1 bit) F9 (1 bit) F10 (1 bit)

0: NextAdrs 0: No action 0: No action

1: InstDec 1: ORmode 1: OR indsrc

Figure 7.23. Format for microinstructions in the example of Section 7.5.3.

Implementation of the Microroutine
Octal
address F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10

0 0 0 0 0 0 0 0 0 0 1 0 0 1 01 1 0 0 1 0 0 0 0 01 1 0 0 0 0
0 0 1 0 0 0 0 0 0 1 0 0 1 1 00 1 1 0 0 0 0 0 0 00 0 1 0 0 0
0 0 2 0 0 0 0 0 0 1 1 0 1 0 01 0 0 0 0 0 0 0 0 00 0 0 0 0 0
0 0 3 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 0 0 1 1 0

121 0 1 0 1 0 0 1 0 1 0 0 01 1 0 0 1 0 0 0 0 01 1 0 0 0 0
122 0 1 1 1 1 0 0 0 0 1 1 10 0 0 0 0 0 0 0 0 00 0 1 0 0 1

1 7 0 0 1 1 1 1 0 0 1 0 1 0 00 0 0 0 1 0 0 0 0 01 0 1 0 0 0
1 7 1 0 1 1 1 1 0 1 0 0 1 0 00 0 1 0 0 0 0 0 0 00 0 0 0 0 0
1 7 2 0 1 1 1 1 0 1 1 1 0 1 01 1 0 0 0 0 0 0 0 00 0 0 0 0 0
1 7 3 0 0 0 0 0 0 0 0 0 1 1 10 1 0 0 0 0 0 0 0 00 0 0 0 0 0

Figure 7.24. Implementation of the microroutine of Figure 7.21 using a

next-microinstruction address field. (See Figure 7.23 for encoded signals.)
 R15in R15out R0 in R0out

Decoder

Decoder

IR Rsrc Rdst

InstDecout
External
inputs ORmode
Decoding
circuits
Condition ORindsrc
codes

AR

Control store

Next address F1 F2 F8 F9 F10

Rdst out

Rdst in
Microinstruction
decoder
Rsrc out

Rsrc in

Other control signals

Figure 7.25. Some details of the control-signal-generating circuitry.

bit-ORing