Lecture 11

Input Output Systems

CS311-Computer Organization Input Output Systems Lecture 11 - 1

 Lecture 11:
Input/Output System
In this lecture, we will study
– Differences between I/O devices and memory
– Basic I/O and I/O system with I/O controller
– Bus
– Protocol
– Bus arbitration
– I/O Interface
– I/O Controller
» DMA, Channel
– I/O System
» Memory mapped I/O
» CPU controlled I/O
» DMA controlled I/O
» Channel controlled I/O
» I/O Processor

CS311-Computer Organization Input Output Systems Lecture 11 - 2

 I/O Device and Memory

• Input: Memory <= Input Device

• Output: Output Device => Memory
• Difference between I/O device and memory
– Operating Speed
» In general, speed of I/O devices is slow than memory
– Unit of information
» Memory: Word
» I/O Device: Byte
– Autonomy
» Memory is synchronized to CPU clock
» I/O devices usually operate asynchronously since they are inherently
slow and distance apart from memory(sending CPU clock is expensive)
– Error rate
» Error rate of I/O Device is much higher than memory

CS311-Computer Organization Input Output Systems Lecture 11 - 3

 Input Output Control
• I/O device controller
– Controls the functions of I/O device
– Sometimes it is integrated into the I/O device
– e.g. Disk Controller
» Moves head to the desired location on the disk surface
» Activates the head to read/write access
» Sometimes one controller controls many disk drives
• I/O controller
– Controls the data moves during I/O
» Notify an I/O device to initiate the operation and notify the completion of I/O
operation to CPU
» Establish a connection between memory and an I/O device for data move
» Checking the status of I/O operation
» Access memory
– e.g. CPU, DMA controller, Channel controller, I/O processor, Front end
processor

CS311-Computer Organization Input Output Systems Lecture 11 - 4

 Basic I/O System

Function of I/O Control is included in CPU

Memory
I/0 I/0 I/0 I/0
Device Device Device Device

Memory I/O Dev I/O Dev I/O Dev

Bus Controller Controller Controller

Interface Interface ... Interface

CPU

I/O Bus
I/O Controller

CS311-Computer Organization Input Output Systems Lecture 11 - 5

 I/O System with I/O
Controller
I/O I/O I/O I/O
Dev Dev Dev Dev

Memory I/O Dev I/O Dev I/O Dev

Controller Controller Controller

Interface Interface Interface

I/O
Memory Controller I/O Bus
Bus
I/O I/O Bus
Controller
Interface Interface Interface

I/O Dev I/O Dev I/O Dev

CPU Controller Controller Controller

I/O I/O I/O I/O

Dev Dev Dev Dev

CS311-Computer Organization Input Output Systems Lecture 11 - 6

 Bus

Device Device Device ... Device

Bus
Device
– Master Device
» Acquires the right to use the bus
» Performs control operation for actual data transmission
– Slave Device
» Perform data transmit operation required by the master device

– In an instance when a data transmission takes place, one device is the

master, and another is the slave. But the roles of device may change.
– Some device can be a master in one instance and a slave in other instance

CS311-Computer Organization Input Output Systems Lecture 11 - 7

 Bus Components

• Data Bus
• Address Bus
• Control Bus
– Master sends Control signals and receives status
signals
In an economical system,
Master Slave One bus can be multiplexed
to send Data and Address

Control Bus
Address Bus
Data Bus

CS311-Computer Organization Input Output Systems Lecture 11 - 8

 Input Output Bus

Independent I/O Bus Memory-I/O Common Bus

CPU I/O
CPU
Dev

I/O
Dev Memory-I/O Common Bus
Memory Bus
...
I/O
Memory I/O I/O I/O
Dev Memory Dev Dev Dev
I/O Bus

CS311-Computer Organization Input Output Systems Lecture 11 - 9

 Protocol

Protocol
Communication between devices with widely different
characteristics require a communication rule called Protocol
– Synchronous Protocol
– Asynchronous protocol

CS311-Computer Organization Input Output Systems Lecture 11 - 10

 Synchronous Protocol
Synchronous Protocol
– Master and Slave devices operate in a synchronized fashion
– Information(bit, character, block) is synchronized with the clock pulse
– Two different methods
» Master sends the clock pulse to the slave with the information
> Suitable for short distance
» Master and Slave both have the synchronized clock pulse
generators which are periodically synchronized
> Suitable for long distance communications
Start Reading Read Complete
Clock Pulse
Address

Data
R/W
WAIT

CS311-Computer Organization Input Output Systems Lecture 11 - 11

 Asynchronous Protocol:
Serial Transmission

Asynchronous Serial Transmission Protocol

0 1 0 1 1 1 0 0 1 1 1 ...

No transmission Data Bits More than 1 Stop Bits

Start Bit

– Master and Slave devices must know

» Number of bits in a unit of information(byte)
» Transmission rate: bit/sec(Baud rate)

CS311-Computer Organization Input Output Systems Lecture 11 - 12

 Asynchronous Protocol:
Parallel Transmission - Handshaking Protocol

Asynchronous Parallel Write Transmission

Request Acknowledge
1
Address Address Next Address
2
Data Data Next Data

R/W 3 Next R/W

W

Req 4
5
Ack

CS311-Computer Organization Input Output Systems Lecture 11 - 13

 Asynchronous Protocol:
Parallel Transmission - Handshaking Protocol

Asynchronous Parallel Read Transmission

1
Address Address Next Address

Data 4 Data Next Data

R/W 2 Next R/W

R

Req 3
5
Ack

CS311-Computer Organization Input Output Systems Lecture 11 - 14

 Bus Arbiter
Bus Arbitration
• In one instance, allow only one master to use the bus
• Provides the fairness of the bus use amongst the devices
– e.g. priority
• 3 bus signals
– Bus Request(BR): bus master sends BR to get the right to use the bus
– Bus Grant(BG): bus arbiter sends BG to requesting bus master as an
authorization of the right to use the bus
» A requestor amongst other requestors based on the established fairness rule(e.g.,
priority)
– Bus Busy(BB): the requestor who has the right to use the bus sends BB to
notify that bus is in use
• 3 different bus arbiter structures
– Centralized Parallel Arbitration
– Serial Arbitration or Daisy Chain arbitration
– Polling Arbitration

CS311-Computer Organization Input Output Systems Lecture 11 - 15

 Centralized Parallel
Arbitration
Bus Arbiter
(Arbitration Algorithm)

BR BB BG BR BB BG BR BB BG

Device 0 Device 1 ... Device n-1

Data Bus

CS311-Computer Organization Input Output Systems Lecture 11 - 16

 Daisy Chain Arbitration

Bus Priority(Arbitration Algorithm)

Device 0 Device 1 Device n

BG BGi BGo BGi BGo ... BGi BGo
Bus Arbiter

BR
BB

Data Bus

• Low priority device may have a danger of starvation

• Serial with daisy chain: when there is a failure in the device in the middle of
the chain, or broken connection between BGi and BGo, the devices beyond
the failing device cannot use the bus

CS311-Computer Organization Input Output Systems Lecture 11 - 17

 Polling Arbitration

Bus Arbiter Device 0 Device 1 ... Device n

BR
BB
Polling Count
Polling Count Order is the Priority order

Data Bus

When a bus requesting device gets its device number through polling count,
it send BB to arbiter and use the bus.

Bus granting time may be too long.

CS311-Computer Organization Input Output Systems Lecture 11 - 18

 Input Output Interface

Function of the I/O Interface

• Recognizing address(device address or device code sent
by I/O instruction)
• Resolving the characteristic differences between I/O
devices and Memory(CPU, I/O Controller)
– Speed
– Unit of information
– Autonomy
» Highly functional I/O controllers
» DMA, Channel, IOP, FEP
– Error rate

CS311-Computer Organization Input Output Systems Lecture 11 - 19

 I/O Interface:
Recognizing Device Code
• Since there are many I/O devices, a unique device code is
assigned to each device. It is received by the interface via
address bus.
• In each interface, there is a device code decoder
Address Bus
1
0
1
1
0
1

DEV SEL DEV SEL

1 0

Device 101101 Interface Device 111111 Interface

CS311-Computer Organization Input Output Systems Lecture 11 - 20

 I/O Interface:
Resolving Speed Difference
• Data Buffer and its associated flag
• Receiving data from a slower device - Input
– Faster device cannot take away data in its Input
own speed, it must wait until data is ready to be taken
away
Data Buffer
– When can it take away?
Input
– When the slower device puts the data in the Data Buffer, it
Device
sets the Flag.
Flag
– Data can be taken away from the data buffer when the Flag is
set and reset after the data is taken away for the next data input

• Sending data to a slower device - Output

– Faster device cannot send data in its own speed, it must Output
wait until data is taken by the slower device
– Flag is set by the output device after the data in the Data Data Buffer
Buffer is output so that the next data to be output Output
can be stored in the Data Buffer Device
– New data can be stored in the Data Buffer only when the Flag
Flag is set

CS311-Computer Organization Input Output Systems Lecture 11 - 21

 I/O Interface:
Resolving Information Unit
Difference
• Bit <=> Byte
• Data Buffer
– Input Data Buffer
» Serial-in Parallel-out
– Output Data Buffer
» Parallel-in Serial-out
Input to Memory(or CPU) in parallel

Input Dev
Clock Output Dev

Bit Counter
Output from Memory(or CPU)
Set when 7

Flag

CS311-Computer Organization Input Output Systems Lecture 11 - 22

 I/O Interface:
Resolving High Error Rate
• Parity bit
– Even parity(even number of 1’s in data bits + parity bit)
1011101 1
0011011 0

– Odd parity(odd number of 1’s in data bits + parity bit)

1011101 0
0011011 1

• Echo Back
• Retry and Timeout
• EDC/ECC

CS311-Computer Organization Input Output Systems Lecture 11 - 23

 Parity Generator/Checker

b0b1b2b3b4b5b6 b7

Odd
Parity
Odd Error
Parity

Even
Even Parity
Parity Error

Parity bit generator Parity checker

CS311-Computer Organization Input Output Systems Lecture 11 - 24

 Input Output Controller

• Functions of I/O Controller

– Establishing a connection between I/O Controller and
Memory
– Storing Memory Address, Direction of data
transmission, and Data for memory access
– Memory access
– Establishing connection between I/O Interface and I/O
Controller
– Data exchange with I/O device
– Notify CPU of completion of I/O operation

CS311-Computer Organization Input Output Systems Lecture 11 - 25

 DMAC as an I/O Controller
A DMA input/output transfers a block, a contiguous words, of data(block)

MCR DMAR
MCG DMAG
CPU
INT
DMAC
R/W ADR DATA
data CPU initialize DMAC
... I/O Device Address
Memory Function(R/W)
Bus Memory Starting Address
Number of words
I/O Dev to M connection for
I/O Dev Cycle Steal by
I/O Dev sends DMAR to DMAC
Control Addr Data
DMAC sends MCR to CPU
Bus Bus Bus
I/O Bus CPU sends MCG to DMAC
DMAC send DMAG to I/O Dev
Memory MCR: Memory Cycle Request DMAC send Addr and Func to
MCG: Memory Cycle Grant M
DMAR: DMA Request
DMAG: DMA Grant
CS311-Computer Organization Input Output Systems Lecture 11 - 26
 DMAC:
Cycle Steal
• CPU is continuously accessing memory, i.e., using memory
cycles during program execution
• When a MCR is received, CPU gives the next memory cycle
to DMAC so that the requesting I/O Device can use the
memory cycle without significant delay that may cause lost
data
DMAR DMAR
CPU FET EXE FET EXE FET EXE FET EXE FET ...
M Cycle

Interrupt
FET EXE FET EXE FET …
Interrupt Routine

DMAC DMAC

CS311-Computer Organization Input Output Systems Lecture 11 - 27

 DMAC:
Data Buffer Logic
I/O Data Bus(8)
Interface

Input SL 8 8
Data Buffer(32) Memory
Clock
LDB/RDB
Output LDB for output
SR 8
Byte Counter RDB for input
I/O Data(32) Resets Byte Counter
=3
Reset Data Buffer
Memory Bus Buffer Full when 4B
Byte Counter = 3
Data Buffer Logic SL for input from I/O bus
SR for output to I/O bus
F LDB/RDB
Control Logic
R/W MCR MCG
Memory Data Bus(32)
CPU Memory Control Bus

CS311-Computer Organization Input Output Systems Lecture 11 - 28

 DMAC:
Address Buffer and
Byte Counter Logic

Memory

Address Buffer
Address Buffer Logic +1 Receiving MCG form CPU, either
=0 Word Counter RDB to move Data Buffer to M, or
LDB to move M to Data Buffer
Word Counter Logic -1 When a word in the block is done
for input/output,
LDB/RDB
Control Logic Increment the address
INT MCG Decrement the word counter
When WC = 0
Implies Completion of I/O
CPU Request Interrupt CPU

CS311-Computer Organization Input Output Systems Lecture 11 - 29

 Channel Controller

A channel Input/Output command transfers multiple blocks of

data
Fixed Channel Variable Channel

Channel
CPU CPU Channel I/O
I/O I/O
Channel Channel I/O
Memory I/O I/O DC
Memory Channel
I/O I/O I/O

CS311-Computer Organization Input Output Systems Lecture 11 - 30

Selector and Multiplexer Channel
• Selector Channel
– A channel dedicated to an I/O device usually for a high speed device
• Multiplexer Channel
– A channel is time shared by several sub-channels, where a sub-channel
serves for a slow I/O device. Thus a multiplexer channel serves several
slow devices in the time multiplexed fashion

Sub-channel I/O

Sub-channel I/O
Multiplexer
Channel

Sub-channel I/O

CS311-Computer Organization Input Output Systems Lecture 11 - 31

 Memory Mapped I/O
Address Space Memory Space
0
Input/Output Instruction 1
I/O
No particular I/O instruction Dev 0
Use Load/Store instructions
I/O 9
When 9 <X<100 Dev 1 10 I/O Device 0
Load R, X for input 11 I/O Device 1
12 I/O Device 2
Store R, X for output I/O
Dev 2 13 I/O Device 3
...

... 99 I/O Device 89

100

I/O
Dev 89
n-1

CS311-Computer Organization Input Output Systems Lecture 11 - 32

 CPU Controlled I/O:
Programmed
Programmed I/O
I/O -- Input
Input
Most elementary I/O
– using B(busy) and D(done) flags
n
[1] If B=1, Repeat [1]; B=0?
[2] B 1;
[3] If D=0, Repeat [3]; y
[4] R Input Data Buffer, D 0; B 1
[5] If there is more input data goto [3]; n
[6] B 0, end; D=1?
Loop1: SBZ X /Skip if B=0 y
JMP Loop1
R Buf, D 0
START X /B 1
Loop2: SDO X /Skip if D=1 n
JMP Loop2 End?
IN R, X
Wasting a lot of y
(M R)
(n n-1) cycles here,depending B 0
(if n>0, JMP Loop2) on the speed of input device
STOP X /B 0

CS311-Computer Organization Input Output Systems Lecture 11 - 33

 CPU Controlled I/O:
Programmed I/O - Output
Most elementary I/O
– using B(busy) and D(done) flags
n
[1] If B=1, Repeat [1]; B=0?
[2] B 1;
[3] If D=0, Repeat [3]; y
[4] Output Data Buffer R, D 0; B 1
[5] If there is more input data goto [3]; n
[6] B 0, end; D=1?
Loop1: SBZ X /Skip if B=0 y
JMP Loop1
Buf R, D 0
START X /B 1
Loop2: SDO X /Skip if D=1 n
JMP Loop2 End?
OUT R, X
Wasting a lot of y
(R M)
(n n-1) cycles here,depending B 0
(if n>0, JMP Loop2) on the speed of input device
STOP X /B 0

CS311-Computer Organization Input Output Systems Lecture 11 - 34

 CPU Controlled I/O:
Programmed I/O
• Inefficient because CPU wastes a lot of cycles simply waiting for the slow I/O device
to respond
• Example
Speed of CPU = 100 MIPS: Assume that identical instruction execution time
Input 1,000 characters from a keyboard, 1 character input time is 1 sec.
How many times SDO instruction in Loop2 will be executed per character input ?

100 MIPS implies that execution time of an instruction is 10 -8 sec.

To simplify the problem, neglect the first three instructions and the last instruction since they
are executed only once at the beginning and at the very last.
Let X be the number of executions of SDO instruction in Loop2.

Number of instruction executions for one character input becomes;

X + (X-1) + 4
Thus, (2X + 3) x 10-8 sec = 1 sec
Therefore, X = 5 x 107 , i.e., it will be executed 50 million times

CS311-Computer Organization Input Output Systems Lecture 11 - 35

 CPU Controlled I/O:
Interrupt Processed I/O

Interrupt processed I/O allows to utilize the slow I/O device’s

response time for the productive work, if there is any

Loop1: SBZ X Waste of CPU cycles Loop1: SBZ X

JMP Loop1 in programmed I/O JMP Loop1
START X START X
Loop2: SDO X Loop3: ION X
JMP Loop2
By allowing Device X ( Execute other tasks
IN R, X to interrupt CPU when ………….. )
(M R) data buffer is ready,
(n n-1) this much CPU cycles IN R, X
(if n>0, JMP Loop2) can be utilized for the (M R)
STOP X productive work. (n n-1)
(if n>0, JMP Loop3)
STOP X
Interrupt from X
Done in the
interrupt processing routine
CS311-Computer Organization Input Output Systems Lecture 11 - 36
 DMAC Controlled I/O
• CPU must send DMAC with
– Direction of data transfer, i.e., Function(R or W)
– Starting address of the block
– Word count
– (Address of DMAC), I/O device address
– (Data block address in I/O device)

• Instruction
– Output instruction if programmed I/O system is used
– ST instruction if memory mapped I/O system is used

CS311-Computer Organization Input Output Systems Lecture 11 - 37

 Channel I/O
• Channel Program stored in memory
– Channel program consists of a linked list of Channel Command
Words(CCW)

CCW0

CCW

CCW

CCW
n
1

2
CAW ...
• Instruction
– START Cn, Dn
• CAW
• CCW
– Information provided to DMAC about data block and direction of transfer

CS311-Computer Organization Input Output Systems Lecture 11 - 38

 Input Output Processor

Input/Output Processor
– Handling of Data to be input/output
– Editing, Debugging, Validating, …
– 2 kinds of I/O Processors(computers)
» Off-line I/O computers
» On-line I/O computers
Off-line
Main Computer Dedicated I/O Computer
Mag Tape Mag Tape
Printer
CPU CPU
Graphics
Dev
Memory Memory
On-line Computer
Disk Disk

CS311-Computer Organization Input Output Systems Lecture 11 - 39

 On-line I/O Computers
Main Computer I/O Computer
Printer

CPU CPU
Graphics
Dev

Memory Memory Computer

Disk

Main Computer I/O Computer

Printer

CPU CPU
Graphics
Dev

Memory Memory Computer

CS311-Computer Organization Input Output Systems Lecture 11 - 40