ONLINE CLASS (2021-22)

PROGRAMMING IN HDL(SEC1406)

MENTORS
Dr.T.RAVI
Dr.T.VINO
Department of ECE
Sathyabama Institute of Science and Technology
SYLLABUS
Course Outcome
After the completion of course student will be able to

CO1 Understand the requirements of VHDL design flow

CO2 Interpret the Verilog language elements and its relevance to
digital design
CO3 Apply the Modelling Styles for Simulation, Synthesis and
Test Bench Creation.
CO4 Analyse the Performance Study of Combinational and
Sequential logic design using Verilog
CO5 Evaluate State Machine and Memory designs by Verilog
CO6 Create and realize the system in FPGA using Verilog
VLSI DESIGN FLOW
 UNIT 2

INTRODUCTION TO VERILOG HDL

HDL – Hardware Description Language
1. VHDL
2. Verilog HDL

VHDL
V H SIC Very High Speed Integrated Circuit
Hardware Description Language

Verilog HDL
Verilog HDL is a Hardware Description Language, that
can be used to model a digital system at many levels of
abstraction ranging from the algorithmic level to
the gate-level to the switch level
Facts About Verilog HDL
We use Verilog for FPGA programming
 Verilog is more popular in industry
 They offer similar features like VHDL
History of Verilog
 In 1980s, originally developed by Gateway Design Automation
 In 1990, was put in public domain
 In 1995, adopted as an IEEE standard 1364-1995
In 2001, an enhanced version, Verilog 2001

Functions of Verilog
 Design entry, like schematic
 Simulation and verification of Design


Verilog HDL
 Synthesis is the process of translating a design description to another
level of abstraction, i.e, from behaviour to structure.

 Synthesis is a process where a HDL is compiled and mapped into an

implementation technology such as an FPGA or an ASIC. Many FPGA
vendors have free (or inexpensive) tools to synthesize HDL for use with
their chips, where ASIC tools are often very expensive.

Verilog HDL Modeling

4 Different Styles of Description
– Structural Modeling

– Data flow Modeling

– Behavioral Modeling
– Mixed Modeling
 Verilog HDL Usage

Verilog may be used to model circuits and behaviors at various levels of



abstraction:
 Transistor/Switch Level Modeling. LOW LEVEL
 Gate Level Modeling.
 Data Flow Modeling.
 Behavioral or algorithmic Modeling. HIGH LEVEL
Verilog HDL – Major Capabilities
 Primitive logic gates- and, or and nand are built-in into the
language
 Flexibility of creating Used Defined Primitives (UDF)
 Switch level modeling primitive gates, such as pmos and
nmos are built-in into the language.
 Three style of modeling
 Two data types – Net data type and Register data type
 Hierarchical design – up to any level, using module
instantiation
 Design – switch level to algorithmic level
VHDL - Verilog HDL

VHDL Verilog HDL

It is dependent on Library Independent on Library

The program body consist of Entire body is defined as
two part. module
Interfacing part (Entity)
Architecture Part Arch. Body)

Case Insensitive Case Sensitive

Free format language Structural language (like ‘C’)

*.VHDL *.v
Verilog HDL
 Basic Unit – A module

 Module
 Describes the functionality of the design
 States the input and output ports

 Example: A Computer
 Functionality: Perform user defined computations
 I/O Ports: Keyboard, Mouse, Monitor, Printer
Basic unit --Module
module module_name (port_name);
port declaration
data type declaration
module functionality or structure
endmodule
 Module  Example (HalfAdder)
General definition
module HalfAdder (A, B, Sum Carry);
module module_name ( port_list );
input A, B;
port declarations;
output Sum, Carry;
…
assign Sum = A ^ B;
variable declaration; //^ denotes XOR
… assign Carry = A & B;
description of behavior // & denotes AND

endmodule endmodule
 Verilog HDL

Example of Adder
 A Full Adder
module name
module adder (carry, sum, a, b, cin); b
a
U0 sum
output carry, sum; I/O pins
cin

input a, b, cin; a
w0
wire w0, w1, w2; u0(su I/O pin declaration
U1

xor m, a, b, cin); ba
U2
w1 U4 carry
and u1(w0, a, b); cin
b
and u2(w1, b, cin); cin
U3 w2

and u3(w2, cin, b);

or u4(carry, w0, w1, w2)
endmodule logic circuit description

build-in module invoked instantiation

<##
 A Simple Verilog Example
// A simple example comment line
module gate1 (a,b,c); module name
input a,b; port list
port declarations
output c; gate1

and (c,a,b); a
c
endmodule end module
b
 Modules are the basic building blocks in Verilog.
 A logic circuit  module, Its ports: inputs and outputs

 Begins with module, ends with endmodule

www.iiu.edu.pk 6 Sunday, May 17, 2015

 Data Flow Modeling

a g f
b
F = AB + B'C

h i

//
// Data
Data Flow
Flow Modeling
Modeling

module
module ex1
ex1 (a,b,c,f);
(a,b,c,f);
input
input a,b,c;
a,b,c; output
output f;
f;
assign
assign ff == (a&b)
(a&b) || (~b&c);
(~b&c);
endmodule
endmodule

1 Sunday, May 17, 2015

7
 Gate Level Modeling

module eg1 (a,b,c,f);

input a,b,c;
output f; a g f
wire g,h,i; b
F = AB + B'C
and (g,a,b);
h i
not (h,b);
and (i,h,c); c

or (f,g,i);
endmodule
Behavioral Styles

a
Black Box out
b 2x1 MUX

sel
 Modeling in Verilog HDL (Ex:Full Adder)
// Full adder Data flow Modeling // Full adder Structural Modeling // Full adder Behavioral Modeling
module fulladd (a, b, c, sum, carry); module fulladd (a, b, c, sum, carry); module fulladd (a, b, c, sum, carry);
input a; input a; input a;
input b; input b; input b;
input c; input c; input c;
output sum; output sum; output sum;
output carry; output carry; output carry;
assign sum = a^b^c; wire p,q,r; reg sum,carry;
assign carry = (a & b) | (b & c) | (c & a); xor reg p,q,r;
endmodule x1(sum,a,b,c); always @ (a or b or c) begin
and sum = (a^b)^c;
a1(p,a,b), p=a & b;
x1 a2(q,b,c), q=b & c;
a3(r,a,c); r=a & c;
or carry=(p | q) | r;
o1(carry,p,q,r); end
rr
a3 endmodule endmodule
a1 p o1
a2 qq
 Data flow Modeling in // Full adder - VHDL
library IEEE;
Verilog HDL & VHDL use IEEE.STD_LOGIC_1164.ALL;
(Ex:Full Adder) use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
// Full adder Data flow – Verilog HDL entity fadd_dataflow is
module fulladd (a, b, c, sum, carry); Port ( a : in std_logic;
input a; b : in std_logic;
input b; c : in std_logic;
sum : out std_logic;
input c;
carry : out std_logic);
output sum;
end fadd_dataflow;
output carry; architecture dataflow of fadd_dataflow is
assign sum = a^b^c; signal p,q,r:std_logic;
assign carry = (a & b) | (b & c) | (c & a); begin
endmodule p<= a and b;
q<= b and c;
x1 r<= c and a;
sum<= ((a xor b) xor c);
carry<= p or q or r;
a3 rr end dataflow;

a1 p o1
a2 qq
 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Structural Modeling in use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Verilog HDL & VHDL entity fadd_structural is
Port ( a : in std_logic;
(Ex:Full Adder) b : in std_logic;
c : in std_logic;
// Full adder – Verilog HDL sum : out std_logic;
carry : out std_logic);
module fulladd (a, b, c, sum, carry); end fadd_structural;
input a; architecture structural of fadd_structural is
input b; component xor2
port(a,b:in std_logic;
input c;
z:out std_logic);
output sum; end component;
output carry; component and2
wire p,q,r,s; port(a,b:in std_logic;
z:out std_logic);
xor end component;
x1(p,a,b), component or3
x2(sum,p,c); port(a,b,c:in std_logic;
z:out std_logic);
and end component;
a1(q,a,b), signal p,q,r,s:std_logic;
a2(r,b,c), begin
x1: xor2 port map (a,b,p);
a3(s,a,c);
x2: xor2 port map (p,c,sum);
or a1: and2 port map (a,b,q);
o1(carry,q,r,s); a2: and2 port map (b,c,r);
endmodule a3: and2 port map (c,a,s);
o1: or3 port map (q,r,s,carry);
end structural;
 library IEEE;
Behavioral Modeling in use IEEE.STD_LOGIC_1164.ALL;
Verilog HDL & VHDL use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
(Ex:Full Adder) entity fadd_behv is
Port ( a : in std_logic;
b : in std_logic;
// Full adder Behavioral Modeling
module fulladd (a, b, c, sum, carry); c : in std_logic;
input a; sum : out std_logic;
input b; carry : out std_logic);
input c; end fadd_behv;
output sum; architecture Behavioral of fadd_behv is
output carry; begin
reg sum,carry; process(a,b,c)
reg p,q,r; variable p,q,r:std_logic;
always @ (a or b or c) begin begin
sum = (a^b)^c; p:= a and b;
p=a & b; q:= b and c;
q=b & c;
r:= c and a;
r=a & c;
sum<= a xor b xor c;
carry=(p | q) | r;
end carry<= p or q or r;
endmodule end process;
end Behavioral;
 Delays
Dataflow Modeling
 Uses continuous assignment statement (Concurrent Statements)
 Format: assign [ delay ] net = expression;
 Example: assign sum = a ^ b;

 Delay: Time duration between assignment from RHS to LHS

 All continuous assignment statements execute concurrently

// Full adder Data flow Modeling

 Order of the statement does not impact the design module fulladd (a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
assign sum = a^b^c;
assign #2 carry = (a & b) | (b & c) | (c & a);
endmodule
 Delays (Cont….)
Dataflow Modeling
 Delay can be introduced
 Example: assign #2 sum = a ^ b;
 “#2” indicates 2 time-units
 No delay specified : 0 (default)

 Associate time-unit with physical time

 `timescale time-unit/time-precision
 Example: `timescale 1ns/100 ps

 Timescale
`timescale 1ns/100ps
 1 Time unit = 1 ns
 Time precision is 100ps (0.1 ns)
 10.512ns is interpreted as 10.5ns
 Delays (Cont….)
Dataflow Modeling

 Example:

`timescale 1ns/100ps
module HalfAdder (A, B, Sum, Carry);
input A, B;
output Sum, Carry;
assign #3 Sum = A ^ B;
assign #6 Carry = A & B;
endmodule
Behavioral Modeling

 Example:

module mux_2x1(a, b, sel, out);

input a, b, sel;
output out;
always @(a or b or sel)
begin
if (sel == 1)
out = a;
else out = b;
end
endmodule
 Behavioral Modeling (Cont…)
 always statement : Sequential Block

 Sequential Block: All statements within the block are executed sequentially

 When is it executed?
 Occurrence of an event in the sensitivity list
 Event: Change in the logical value

 Statements with a Sequential Block: Procedural Assignments

 Procedural Assignments may optionally have a delay

 Inter-Statement Delay
 Intra-Statement Delay
Behavioral Modeling (Cont…)
 Inter-Assignment Delay
 Example:
Sum = A ^ B;
#2 Carry = A & B;
 Delayed execution

 Intra-Assignment Delay
 Example:
Sum = A ^ B;
Carry = #2 A & B;
 Delayed assignment
 Procedural Constructs

 Two Procedural Constructs

 initial Statement
 always Statement
 initial Statement : Executes only once
 always Statement : Executes in a loop
 Example:
… …
initial begin always @(A or B) begin
Sum = 0; Sum = A ^ B;
Carry = 0; Carry = A & B;
end end
… …
 // VHDL example
library IEEE;
Structural Modeling use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
(Ex:Full Adder) use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_structural is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_structural;
architecture structural of fadd_structural is
component xor2
port(a,b:in std_logic;
 Instantiation: z:out std_logic);
end component;
component and2
 Positional Association port(a,b:in std_logic;
z:out std_logic);
 Named Association end component;
component or3
port(a,b,c:in std_logic;
z:out std_logic);
end component;
signal p,q,r,s:std_logic;
begin
x1: xor2 port map (a,b,p);
x2: xor2 port map (p,c,sum);
a1: and2 port map (a,b,q);
a2: and2 port map (b,c,r);
a3: and2 port map (c,a,s);
o1: or3 port map (q,r,s,carry);
end structural;
Language Elements of Verilog HDL
 Identifiers
 Comments
 Format
 System Tasks and Functions
 Compiler Directives
 Value Set
 Data Types
 Parameters
 Identifiers of Verilog

 Identifiers are user-provided name for Verilog objects within a

description.
 Legal characters in identifiers:
a-z, A-Z, 0-9, _, $
 The first character of an identifier must be an alphabetical
character (a-z, A-Z) or an underscore ( _ ).

 Identifiers can be up to 1024 characters long.

Example:
Mux_2_1 abc123 ABC123
Sel_ A$b$10
 Escaped Identifiers

 Escaped Identifiers start with a backslash (\) and end with a

white space.
 They can contain any printable ASCII characters.
 Backslash white space are not part of the
and identifiers.
Example:
module \2:1mux(out, a, b, sel);
\7400
\-Q
\(******)
 Comments

// Single line comment

/* Another single line comment */

/* Begins multi-line (block) comment

All text within is ignored
Line below ends multi-line comment
*/
 Format

 Verilog is case sensitive.

 It is a free format language
 Written across single line or multiple lines

initial begin Top = 3’b001; #2 Top = 3’b011; end

initial
begin
Top = 3’b001;
#2 Top = 3’b011;
end
 System Tasks and Functions
 $<identifier>
 Sign‘$’ denotes Verilog system tasks and functions.
 A task can return zero or more values. A function is like a task except that it can
return only one value.
 A number of system tasks and functions
are available to perform different operations such as
• Display tasks
– $display : Displays the entire list at the time when statement is encountered
– $monitor : Whenever there is a change in any argument, displays the entire list at end of time
step
• Simulation Control Task
– $finish : makes the simulator to exit
– $stop : suspends the simulation
• Time -system function
– $time: gives the simulation
 Compiler Directives
• Identifiers that starts with (`) (backquote) character are called compiler directives
 Compiler directives remain active until they are overridden or deactivated.
Verilog Standard compiler directives are
 `define, `undef
 `ifdef, `else, `endif
 `include
 `resetall
 `timescale
 `celldefine, `endcelldefine
 Compiler Directives
 The `resetall compiler directive resets all the compiler directives to
their default values (only if there is a default value).

Compiler Directives Example:

`define s0 2’b00
`include “lib.v”
`timescale 10ns/100ps
`resetall
 Compiler Directives
 The `define compiler directive provides a simple text- substitution
facility.
• Syntax: ‘define <macro_name> <text_string>
• <text_string> will substitute <macro_name> at compile time.

 Typically use ‘define to make the

description more readable.
• Example:
• `define false 0
• …
• assign a = false ; ==> assign a = 0;
• `undef false
 Compiler Directives

• `ifdef, `else, `endif

`ifdef WINDOWS
Parameter Word = 16;
`else
Parameter Word = 32;
`endif
 Compiler Directives

 `include compiler directive to insert the contents of an entire file.

`include “lib.v”
`include “dir/lib.v”

 ‘timescale
`timescale time unit / time precision
Example:
module m1(…);
…
`timescale 100ns/1ns;
…
 Value Set
 Verilog consists of only four basic values. Almost all verilog data
types store all these values:

0 (logic zero ,or false condition)

1 (logic one ,or true condition)
X (unknown logic value)
Z (high impedance state)

• A constant in Verilog HDL is made up of the above four basic

values.
 Value Set
There are three types of constants in Verilog HDL

• Integer
• Real
• String

Integers:
Reals: String:
Simple decimal
32 is Decimal Notation Sequence of characters
decimal 32 2.0 with in double quotes.
-15 is
decimal -15 5.678 “INTERNAL ERROR”

Base Format Notation Scientific Notation

[size] ‘base value 3.6E2 360.0
5’O37 5-bit
 DATA TYPES

 The set of verilog HDL data types is designed to

represent data storage and transmission
elements found in digital hardware.

 Net type:
• It represents physical connection between structural
elements.
• Net default value is z

 Register type:
• It represents a data storage element.
• Register type default value of x.
 Nets and Registers
 Nets: nets are continuously driven by the devices that drive them.
 wire, wor, wand, ...
- example : wire p; //scalar type

wire [7:0] w1,w2;

wire [0:7] w1; //vector type

- if wire is not vector type, then it doesn’t need to declaration.

 Registers: registers are used extensively
in behavioral modeling and in applying
stimulus.
 reg
- example: reg [3:0] variable; reg[3:0]p;
 Net Type
 Various net types are available for modeling design-
specific and technology-specific functionality.

Net Types Functionality

wire, tri
wor, trior For multiple drivers that are Wired-OR
wand, triand For multiple drivers that are Wired-AND
trireg For nets with capacitive storeage
tri1 tri0 For nets with weak pull up device For
supply1 nets with weak pull down device Power
supply0 net Ground net
 True Tables for tri, triand, and trior Net
s

wand/triand – wired–and net

wor/trior – wired-or net
 Register Type

Five different kinds of register types

• reg
• integer
• time
• real
• realtime
 Reg Register
• A value in a reg register is unsigned number.
• Example:
reg sum, carry, p,q; //one bit register
reg [3:0] Q; // Q is four bit register

Memories:
Memory is an array of registers.
reg[0:3] mymem [0:63] // an array of 64, 4 bit register
 Registers
Integer Register
•An integer register contains integer values. It can be used as a general purpose
register.
•An integer cannot be accessed as a bit-vector.
•The size of an integer variable is 32 bits.
Integer a,b,c; // three integer register
integer p[0:3]; //An array of four register

Time Register:
•A time register is used to store and manipulate time values.
time events [0:31]; // Array of time values
time currtime // holds one time value
 PARAMETERS

 Verilog parameters do not belong to either the

register or the net group.

 Parameters are not variables, they are constants.

 The syntax for parameter declaration is as follows:

parameter msb=7; //defines msb as a constant value 7

parameter e=25,f=9; //defines two constant numbers
 OPERANDS
• Constant
• Parameter
• Net
• Register
• Bit-select
• Part select
• Memory element
Operators Used in Verilog
 Operators Used in Verilog (Cont.)
 The Relational Operators Defined

 The Equality Operators Defined

Equality and Identity Operators
 Logical Operators

 &&  logical AND

 ||  logical OR
 !  logical NOT
 Operands evaluated to ONE bit value: 0, 1 or x
 Result is ONE bit value: 0, 1 or x
A = 1; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x
but
butC&&B=0
C&&B=0
 Bitwise Operators

&  bitwise AND

|  bitwise OR
~  bitwise NOT
^  bitwise XOR
 ~^ or ^~  bitwise XNOR

 Operation on bit by bit basis

 Bitwise Operators (Example)
c = ~a; c = a & b;

 a = 4’b1010;
b = 4’b1100;

c = a ^ b;

 a = 4’b1010;
b = 2’b11;
 shift, Conditional Operator

 >>  shift right

 <<  shift left
 a = 4’b1010;
d = a >> 2;// d = 0010,c = a << 1;// c = 0100
 cond_expr
A ? true_expr : false_expr
1
Y
B Y = (sel)? A : B;
0
sel
 Concatenation and Replication Operators

 Concatenation is the operation of joining bits from smaller expressions to form larger
expressions.
{exp1, exp2, …. expN}

 Replication is performed by a repetition number.

{repetition _number {exp1, exp2, ….expN}
Example:
{3{1’b1}} is 111
{3{ack}} is same as {ack, ack, ack}