EE-16102: MICROPROCESSOR & COMPUTER ORGANIZATION

8085 Microprocessor: Instruction Cycle

Dr. Vishal Kumar Gaur

Microprocessor: 8085A
Instruction Cycle

 Any instruction has two parts: Opcode and Operand

 To execute any instruction μP has to pursue the following steps:
1. Instruction has to be fetched.
2. Decode the instruction using instructor decoder.
3. Perform the function specified by the decoded instruction.

Fetch Decode Execute

Instruction Cycle
 To execute an instruction, microprocessor has to perform various operations such as memory Read/Write,
I/O Read/Write, and sometimes also request acknowledge.

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Microprocessor: 8085A
Instruction Cycle

 All these operations are performed during execution of a instruction within a given time interval, which is
provided by the clock of the system.
 With reference to the mentioned operations (fetch, decode, and execute) certain terms can be defined.

Fetch Decode Execute

Instruction Cycle

 Instruction Cycle, Machine Cycle, and T-states or Clock Cycles

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Microprocessor: 8085A
Instruction Cycle

1. Instruction Cycle: Time required for completing the execution of an instruction is known as instruction
cycle. The 8085 instruction cycle consists of one to six machines cycles or operations.

2. Machine Cycle: It is the time required for completing a single operation. This operation can be accessing
memory for read/write operation or accessing I/O device. There can be 3 to 6 clock periods or T-states in a
machine cycle.

3. T-states or Clock Cycles: T-state is equivalent to one clock period. One clock period, i.e. the period
between two negative going transitions of that clock is called T-state. It is the time in which only a
subdivision of the operation can be performed. Hence, each machine cycle contains a number clock cycles
or T-states.

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Microprocessor: 8085A
Instruction Cycle

Timing Diagrams
 A timing diagram of an instruction is a graphical representation of the time taken by the μP to fetch,
decode, and execute an instruction.
 The size of instruction and frequency of μP decides the total amount of time taken to execute an
instruction.

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Microprocessor: 8085A
Instruction Cycle

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Microprocessor: 8085A
Instruction Cycle

 The number of machine cycles required to execute the instruction depends on the particular instruction.

 Some of the instructions require no additional machine cycles after the instruction fetch is complete. Such
instruction have only one machine cycle in instruction cycle.

 Other instructions may requires additional machine cycles to write or read data to or from memory or I/O
devices.

 Hence, the total number of machine cycles required varies from one to five.

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  Two status signals (S1 and S0) along with IO/M signal output
Microprocessor: 8085A identify the type of the machine cycle being executed by the
8085.
 These signals are issued (or become valid) at the beginning of
the machine cycle and remain stable throughout the machine
Instruction Cycle
cycle.

There are seven kinds of Machine Cycles in 8085.

1. Opcode Fetch Machine Cycle (OFMC)
2. Memory Read Machine Cycle (MRMC)
3. Memory Write Machine Cycle (MWRMC)
4. I/O Read Machine Cycle (IORDMC)
5. I/O Write Machine Cycle (IOWRMC)
6. Interrupt Acknowledge Machine Cycle (INTAMC)
7. Bus Idle Machine Cycle (BIMC)

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Microprocessor: 8085A
Instruction Cycle

1. Opcode Fetch Machine Cycle (OFMC)

 The instruction fetch portion of an instruction cycle requires a machine cycle for each byte of the instruction
to be fetched.
 The first machine cycle of an instruction cycle is always an OPCODE FETCH machine cycle that requires
either four- or six-clock cycles (T-states).
 Since an instruction consists of 1 to 3 bytes (1, 2 or 3), the instruction fetch is one to three machine cycles
in duration.
 Therefore, one or two memory read machine cycles (MRMC) are also needed to complete the fetch for 2nd
and 3rd bytes of the instruction respectively.
 These other machine cycles that follow OFMC will need three clock cycles (T-states).
 The purpose of an OFMC is to read the contents of a memory location containing the opcode addressed by
the program counter and to place it in the instruction register (IR).

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Microprocessor: 8085A
Instruction Cycle OFMC
MC-1 MC-2
1. Opcode Fetch Machine Cycle (OFMC)
 In the beginning of state T1, the 8085 puts a low on
the IO/M line of system bus indicating a memory
operation.

 The 8085 sets S1=1 and S0=1 on the system bus,

indicating the memory fetch operation. This status
information remains available for the duration of the
machine cycle.

 During T1 state, the 16-bit address A15-A0 of the

memory location containing the opcode is obtained
from the program counter (PC) and placed on the
address and address/data latches.

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Microprocessor: 8085A
Instruction Cycle OFMC
MC-1 MC-2
1. Opcode Fetch Machine Cycle (OFMC)
 The higher order 8-bits of the address appear on the
address bus A8-A15 remains constants until the end of
the state T3. During T4 state the data on the address
bus is unspecified.

 The low order 8-bits of the address are placed on the

address/data bus, AD7-AD0 at the beginning of T1.

 This data however remains valid only until the

beginning of state T2.

 After this time, this time-multiplexed bus is used as the

data bus during T2 and T3 states.
 Therefore, ALE signal issued by the 𝜇𝑝 during T1 is
used to latch this lower order address in some external
latch on its falling edge.

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Microprocessor: 8085A
Instruction Cycle OFMC
MC-1 MC-2
1. Opcode Fetch Machine Cycle (OFMC)
 During state T2, after the RD signal is made low, the
external decoding circuit decodes the address put on
the address bus during T1 state.

 One of the memory location is selected and 8-bit

information (opcode) to be fetched is placed on the
data bus (AD7-AD0).

 Whatever information is available on BDB at LOW to

HIGH transition of RD, that will be read or sent to IR.

 The contents of PC is incremented by 1 during this

state to indicate the next subsequent byte of
instruction, as during T1 state, the PC has sent the
address to address bus.

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Microprocessor: 8085A
Instruction Cycle OFMC
MC-1 MC-2
1. Opcode Fetch Machine Cycle (OFMC)
 The accessed memory should be fast enough to
output its data before RD goes high.
 Slower memories can gain more time by pulling the
READY signal of 8085 LOW.
 This will introduce an integral number of TWAIT states
between T2 and T3 as long as READY is low.
 On the rising edge of the RD control signal in T 3 state,
the opcode obtained from the memory is transferred
to the microprocessor instruction register.

 During state T4, the 8085 decodes the instruction and

enter T1 state of the next machine cycle.

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Microprocessor: 8085A
Instruction Cycle OFMC
MC-1 MC-2
1. Opcode Fetch Machine Cycle (OFMC)

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Microprocessor: 8085A
Instruction Cycle

2. Memory Read Machine Cycle (MRMC)

 The IO/M signal is made LOW to indicate the external
world that a memory reference is required.
 Then 𝜇𝑃 made S0=0 and S1=1 indicating that memory
READ operation is to be performed.
 During T1, the 𝜇𝑃 places the contents of higher byte
of the memory address register, such as that contents
of the (PCH) or (H) register on A15-A8.
 The contents of the lower byte of the memory address
register such as contents of the (PCL) or (L) register
places on AD7-AD0. The 𝜇𝑃 sets
 ALE signal HIGH indicating the beginning of MC-2.
 As soon as ALE goes to LOW in the middle of T1, the
lower byte of the address is latched in an external
latch.
 The same bus is now going to be used as data bus.
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Microprocessor: 8085A
Instruction Cycle

2. Memory Read Machine Cycle (MRMC)

 During T2 state, the RD signal goes LOW indicating a
READ operation.
 If the address sent out during T1 state is from (PC),
then (PC) is incremented by 1 otherwise not.
 The external logic gets the data from the memory
location addressed by the memory address register
such as (H,L) pair and places the data on to bi-
directional data bus AD7-AD0.

 During T3 state, RD signal goes HIGH. This LOW to

HIGH transition of signal transfers the data from the
data bus to internal register such as the accumulator.

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Microprocessor: 8085A
Instruction Cycle

3. Memory Write Machine Cycle (MRWC)

 It also requires only T1 to T3 or three T-states.
 The purpose of memory write machine cycle is to
store the contents of any of the 8085 register such as
the accumulator into a memory location addressed by
a register pair such as (H,L).

 The 𝜇𝑃 made IO/M = 0 in the beginning of T1 state to

indicate memory reference operation.
 Then it puts S0 = 1 and S1 = 0 indicating a memory
write operation.

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Microprocessor: 8085A
Instruction Cycle

3. Memory Write Machine Cycle (MRWC)

 During T1 state, 8085 places the memory address
register (MAR) higher byte such as the contents of the
(H) register on lines A15-A8 and also places the MAR
lower byte such as the contents of the (L) register on
lines AD7-AD0.
 The 𝜇𝑝 sets ALE signal HIGH indicating the beginning
of MWRMC.
 As soon as ALE goes to low, the lower byte of the
address is latched in an external latch.
 During T2 state, WR goes LOW indicating memory
write operation.
 It also places the contents of the internal register, say
accumulator, on data lines AD7-AD0.

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Microprocessor: 8085A
Instruction Cycle

3. Memory Write Machine Cycle (MRWC)

 During T3 state, WR goes HIGH. This LOW to HIGH
transition is used to transfer the data from the data lines
to the memory location address by MAR such as (H,L)
register pair.

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Microprocessor: 8085A
Instruction Cycle

4/5. I/O READ and I/O Write Machine Cycle

 The IORDMC and IOWRMC are identical to MRMC & MWRMC respectively except that appropriate status
signals are issued at the beginning of T1 state.
 IO/M signal goes HIGH at the beginning to indicate I/O device reference is needed in case of I/O mapped
input/output device.
 In these machine cycles higher & lower address bytes are identical and equal to the 8-bit address of the I/O
port while in case of MRMC or MWRMC, the address bus output is the true 16-bits address.

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Microprocessor: 8085A
Instruction Cycle

Example
 Two machine codes-0011 1110H (3EH) and 0011 0010H (32H) are stored in memory locations 2000H and
2001H, respectively, as shown below. The first machine cycle (3EH) represents the opcode to load a data
byte in the accumulator, and the second code (32H) represents the data byte to be loaded in the
accumulator. Illustrate the bus timings as these machine codes are executed. Calculate the time required to
execute the Opcode and memory read cycles and the entire instruction cycle if the clock frequency is 2
MHz.

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Thank You

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