Scribd
Upload
4 views

Computer Organization and Architecture

This document discusses computer organization and Arm microcontrollers. It summarizes that cache memory is a fast type of volatile memory that stores frequently used programs, applications, and data to improve processing speed. It describes how caches work on CPU chips, including primary and secondary caches, hit rates, and access times. Other cache enhancements discussed include write buffers, prefetching instructions, and lookup-free caches that support multiple outstanding misses.

Uploaded by

Bhavya Naik
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
4 views

Computer Organization and Architecture

This document discusses computer organization and Arm microcontrollers. It summarizes that cache memory is a fast type of volatile memory that stores frequently used programs, applications, and data to improve processing speed. It describes how caches work on CPU chips, including primary and secondary caches, hit rates, and access times. Other cache enhancements discussed include write buffers, prefetching instructions, and lookup-free caches that support multiple outstanding misses.

Uploaded by

Bhavya Naik
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 12

Computer Organization

& Arm Microcontroller

Presented By:
Shivani Krishna Naik
2AB21EC019
Caches On The CPU Chip
What is Cache memory?
• Cache memory is a small-sized type of volatile computer memory that
provides high-speed data access to a processor and stores frequently used
computer programs, applications and data.
• Cache memory is used to improve the processing speed and efficiency of
a computer system.

2
Caches On The CPU Chip
• Information is transferred between different chips, considerably delay are
introduced in driver and receiver gates on the chips.
• Here some manufactures have chosen to implement two separate caches,
one for instruction and another for data.
• Other have implemented a single cache for both instruction and data.

3
• A combined cache for instruction and data is likely to have a somewhat better
hit rate, because it offers greater flexibility in mapping new information into
the cache.
• If separate caches are used, it is possible to access both caches at the same
time, which leads to increased parallelism and, hence better performance.
• The size of the cache on the CPU chip is limited by space constraints, a good
strategy for designing a high performance system is to use such a cache as a
primary cache. An external secondary cache, constructed with SRAM chips,
is then added to provide the desired capacity.
• If both primary and secondary caches are used, the primary cache should be
designed to allow very fast access by the CPU, because its access time will
have a large effect on the clock rate of the CPU. The Secondary cache can be
considerably slower, but it should be much larger to ensure all high hit rate.
4
The average access time experienced by the CPU in a
system with two levels of caches is:
• tavg= h1C1 +(1-h1)h2C2 +(1-h1)(1-h2)M
Where as parameters are defined as follows:
h1 is the hit rate in the primary cache.
h2 is the hit rate in the secondary cache.
C1 is the time to access information in the primary cache.
C2 is the time to access information in the secondary cache.
M is the time to access information in the main memory.
5
Other Enhancements
Write Buffer
1.Write through
 Each write operation results in writing a new value into the main memory.
 If the processor has to wait for the write operation to be complete, it
shows down the processor.
 The processor does not depends on the results of the write operation.

6
•To improve the performance a write buffer can be included for
temporary storage of write requests.

•The CPU places each write request into this buffer and continues
execution of the next instruction.

•The write buffer may load the number of write equations. Thus, it is
possible that a subsequent read request may refer to data that are still
in the write buffer .

7
2.Write-back

• In this case ,the write operations are simply performed on the


corresponding word in the cache.
• Block is written back to the main memory when it is replaced.
• If the processor waits for this write to complete, before reading the new
block, it is slow down.
• Fast write buffer can hold the block to be written, and the new block can
be read first.
8
Prefetching
• The new data are brought into the cache when they are first needed and the desired
data loaded from the main memory.
• The CPU has to pause until the new data arrive, which is the effect of the miss penalty.
• To avoid stalling the CPU, it is possible to prefetching the data into the cache before
they are needed. The simplest way to do this is through software.
• A special prefetching instruction may be provided in the instruction set of the
processor.
• A prefetching instruction is inserted in a program to cause the data to be loaded in the
cache by the time they are needed in the program.

9
• Prefetch instructions can be inserted into a program either by the
programmer or by the compiler.
• Some prefetches may load into the cache data that will not be used by the
instructions that follow. This can happen if the prefetched data are ejected
from the cache by a read miss involving other data.
• However, the overall effect of software prefetching on performance is
positive, and many processors have machine instructions to support this
feature.
• Prefetching can also be done through hardware. This involves adding
circuitry that attempts to discover a pattern in memory references, and
then prefetches data according to this pattern.

10
Lookup-Free Cache
• Prefetching scheme does not work if it stops other accesses to the cache until the
prefetch is completed.
• A cache of this type is said to be “locked” while it services a miss.
• Cache structure which supports multiple outstanding misses is called a lockup free
cache.
• Since only one miss can be serviced at a time, a lockup free cache must include
circuits that keep track of all the outstanding misses.
• Special registers may hold the necessary information about these misses.
11
THANK YOU….

12

You might also like