Microcontrollers

Chapter 2
8051 MICROCONTROLER ARCHITECTURE

1
 Chapter 2. 8051 microcontroller architecture
2.1. Introduction to 8051 microcontrollers
2.2. Block diagram and pins
2.3. Memory
2.4. Special function registers
2.5. Reset operation
 Chapter 2. 8051 MICROCONTROLER ARCHITECTURE

2.1
Introduction to
8051
Microcontroler

1
2.1 Introduction to 8051 Microcontroler

1
2.2. Block diagram and pins

 Block diagram:
 Pins 40
VCC 32
30pF P0.7 AD7
19
XTAL1 33 AD6
P0.6
34 AD5
P0.5
12MHz 35 AD4
P0.4
36 AD3
P0.3
18 37 AD2
XTAL2 P0.2
38 AD1
30pF P0.1
39 AD0
P0.0

P1.7 8
29 P1.6 7
PSEN
P1.5 6
5
8051 microcontroller has 40 pins. 30
ALE
P1.4
P1.3 4
31 EA P1.2 3
P1.1 2
9 P1.0 1
RST

P2.7 28 AD15
RD 17 P3.7 27
P2.6 AD14
WR 16 P3.6 26
P2.5 AD13
T0 15 P3.5 25
P2.4 AD12
T1 14 P3.4 24
P2.3 AD11
INT1 13 P3.3 23
P2.2 AD10
INT0 12 P3.2 22
P2.1 AD9
TXD 11
P3.1 P2.0 21 AD8
RXD 10 P3.0
VSS
20
 Pins 40
VCC P0.7
32
AD7
30pF 19
XTAL1 33
P0.6 AD6
34
P0.5 AD5
 P0 (Port 0) 12MHz P0.4
35
36
AD4
P0.3 AD3
 A dual – purpose port on 18
XTAL2 P0.2
37
38
AD2

pins 32 -39. 30pF P0.1

P0.0
39
AD1
AD0

 a general purpose I/O port. P1.7

8
7
 A multiplexed address and 29 PSEN P1.6
P1.5
6

data bus. 30
ALE
P1.4
P1.3
5
4
31 EA 3
P1.2
2
P1.1
1
9 RST P1.0

28 AD15
P2.7
17 P3.7 27
RD P2.6 AD14
16 P3.6
WR 26
P2.5 AD13
15 P3.5 25
T0 P2.4 AD12
14 P3.4
T1 24
P2.3 AD11
13 P3.3 23
INT1 P2.2 AD10
12 22
INT0 P3.2 P2.1 AD9
11
TXD P3.1 P2.0 21 AD8
RXD 10 P3.0
VSS
20
 Pins 40
32
VCC P0.7 AD7
30pF 19
XTAL1 33
P0.6 AD6
34
P0.5 AD5
12MHz 35
P0.4 AD4

 P1 (Port 1) 18
XTAL2
P0.3
P0.2
36
37
AD3
AD2
38

 A I/O port on pins 1-8.

30pF P0.1 AD1
39
P0.0 AD0

8
P1.7
29 7
PSEN P1.6
6
P1.5
5
30 P1.4
ALE 4
P1.3
31 EA 3
P1.2
2
P1.1
1
9 RST P1.0

28 AD15
P2.7
17 P3.7 27
RD P2.6 AD14
16 P3.6
WR 26
P2.5 AD13
15 P3.5 25
T0 P2.4 AD12
14 P3.4
T1 24
P2.3 AD11
13 P3.3 23
INT1 P2.2 AD10
12 22
INT0 P3.2 P2.1 AD9
11
TXD P3.1 P2.0 21 AD8
RXD 10 P3.0
VSS
20
 Pins 30pF 19
40
VCC P0.7
32
AD7
XTAL1 33
P0.6 AD6
34
P0.5 AD5
12MHz 35
P0.4 AD4
 P2 (Port 2) 18
P0.3
P0.2
36
37
AD3
AD2
XTAL2

 pins 21 – 28
38
30pF P0.1 AD1
39
P0.0 AD0

 serving as general purpose 29

P1.7
P1.6
8
7

I/O or as the high byte of 30

PSEN
P1.5
P1.4
6
5

the address bus. 31 EA

ALE
P1.3
P1.2
4
3
2
P1.1
1
9 RST P1.0

28 AD15
P2.7
17 P3.7 27
RD P2.6 AD14
16 P3.6
WR 26
P2.5 AD13
15 P3.5 25
T0 P2.4 AD12
14 P3.4
T1 24
P2.3 AD11
13 P3.3 23
INT1 P2.2 AD10
12 22
INT0 P3.2 P2.1 AD9
11
TXD P3.1 P2.0 21 AD8
RXD 10 P3.0
VSS
20
 40

Pins 30pF 19
XTAL1
VCC P0.7
P0.6
32
33
AD7
AD6
 P3 (Port 3) 12MHz
P0.5
34
35
AD5
P0.4 AD4

 A general – purpose I/O on pins 18

P0.3
P0.2
36
37
AD3
AD2
XTAL2
21 – 28. 30pF P0.1
38
39
AD1
P0.0 AD0
 Each pin has a specical feature. 8
P1.7
7
P3.0 – P3.7 hoặc theo byte P3. 29 PSEN P1.6
P1.5
6
5
30 P1.4
ALE 4
Bit Name Function P1.3
3
31 EA P1.2
2
P3.0 RxD Receive data for serial port P1.1
1
9 RST P1.0
P3.1 TxD Transmit data for serial port
P3.2 INT0 External interrupt 0 17
P2.7
28 AD15
RD P3.7 27 AD14
P2.6
16
P3.3 INT1 External interrupt 1 WR
15
P3.6
P2.5
26 AD13
T0 P3.5 25 AD12
P2.4
P3.4 T0 Timer/ Counter 0 external input T1
14 P3.4
P2.3
24 AD11
13 P3.3 23
INT1 P2.2 AD10
P3.5 T1 Timer/ Counter 1 external input INT0
12
P3.2 P2.1
22 AD9
11
TXD P3.1 P2.0 21 AD8
P3.6 WR External data memory write strobe RXD 10 P3.0
VSS
20
P3.7 RD External data memory read strobe
 Pins 30pF 19
40
VCC P0.7
32
AD7
XTAL1 33
P0.6 AD6
34
P0.5 AD5
12MHz 35
P0.4 AD4
 XTAL1 and XTAL2 18
P0.3
P0.2
36
37
AD3
AD2
XTAL2

 An on – chip oscillator is
38
30pF P0.1 AD1
39
P0.0 AD0

driven by a crystal connected P1.7

8

to pins 18 nad 19. 29 PSEN P1.6

P1.5
7
6
5

The nominal crystal

30 P1.4
ALE 4
P1.3
31 EA 3
P1.2
frequency is 12MHz. 9
P1.1
P1.0
2
1
RST

 The on – chip oscillator 28

needn’t be driven by a RD
WR
17
16
P3.7
P3.6
P2.7
P2.6
27
AD15
AD14
26
crystal. A TTL clock source T0
15
14
P3.5
P2.5
P2.4
25
AD13
AD12

can be connected to XTAL1

T1 P3.4 24
P2.3 AD11
13 P3.3 23
INT1 P2.2 AD10
12

and XTAL2.
INT0 P3.2 22 AD9
P2.1
11
TXD P3.1 P2.0 21 AD8
RXD 10 P3.0
VSS
20
 Pins 30pF 19
40
VCC P0.7
32
33
AD7
XTAL1 P0.6 AD6
34
P0.5 AD5
12MHz 35
P0.4 AD4
 EA (External Access) 18
P0.3
P0.2
36
37
AD3
AD2
XTAL2

Choose the external memory.

38
30pF P0.1 AD1
39
P0.0 AD0

EA=0: Programs execute from 29

P1.7
P1.6
8
7

external memory. 30
PSEN
P1.5
P1.4
6
5
ALE
EA=1: Programs excutes from
4
P1.3
31 EA 3
P1.2
2
internal memory 9 RST
P1.1
P1.0
1

28 AD15
P2.7
17 P3.7 27
RD P2.6 AD14
16 P3.6
WR 26
P2.5 AD13
15 P3.5 25
T0 P2.4 AD12
14 P3.4
T1 24
P2.3 AD11
13 P3.3 23
INT1 P2.2 AD10
12 22
INT0 P3.2 P2.1 AD9
11
TXD P3.1 P2.0 21 AD8
RXD 10 P3.0
VSS
20
 Pins 30pF 19
40
VCC P0.7
32
AD7
XTAL1 33
P0.6 AD6
34
P0.5 AD5
12MHz 35
P0.4 AD4
 PSEN 18
P0.3
P0.2
36
37
AD3
AD2
XTAL2
38
(Program Store Enable) 30pF P0.1
P0.0
39
AD1
AD0

Enable external program 29

P1.7
P1.6
8
7

memory. 30
PSEN
P1.5
P1.4
6
5
ALE
It usuallt connects to Output
4
P1.3
31 EA 3
P1.2
2
Enable pin (OE) of EFROM 9 RST
P1.1
P1.0
1

28 AD15
P2.7
17 P3.7 27
RD P2.6 AD14
16 P3.6
WR 26
P2.5 AD13
15 P3.5 25
T0 P2.4 AD12
14 P3.4
T1 24
P2.3 AD11
13 P3.3 23
INT1 P2.2 AD10
12 22
INT0 P3.2 P2.1 AD9
11
TXD P3.1 P2.0 21 AD8
RXD 10 P3.0
VSS
20
 Pins 30pF
40
VCC P0.7
32
AD7
19
XTAL1 33
P0.6 AD6
34
P0.5 AD5
12MHz 35
P0.4 AD4
ALE 18
P0.3
P0.2
36
37
AD3
AD2
XTAL2
38
(Address Latch Enable) 30pF P0.1
P0.0
39
AD1
AD0

 demultiplexing the 29
P1.7
P1.6
8
7

address and data bus. 30

PSEN
P1.5
P1.4
6
5
ALE 4
P1.3
31 EA 3
P1.2
2
P1.1
1
9 P1.0
D0 – D7 RST

28
A0 – A7 RD
17 P3.7
P2.7
27
AD15
P2.6 AD14
D Q WR
16 P3.6
P2.5
26 AD13
P0 (AD0 – AD7) T0
15 P3.5 P2.4
25 AD12
14 P3.4
T1 24
P2.3 AD11
13
G INT1
12
P3.3 P2.2
23
AD10
INT0 P3.2 22
ALE TXD
11
P3.1
P2.1 AD9
21 AD8
P2.0
RXD 10 P3.0
VSS
20
 Pins
ALE D0 – D7

(Address Latch Enable) A0 – A7

D Q
 When Port 0 is used as the P0 (AD0 – AD7)
data bus, ALE latches the G
address into an external ALE
register during the first half of
a memory cycle. During the
second half of the memory
cycle Port 0 lines are avaiable
for data input and output.
The ALE signal pulse at
f=1/6fclock
 Pins 40
VCC 32
30pF P0.7 AD7
19
33
 RST (Reset)
XTAL1 P0.6 AD6
34
P0.5 AD5
12MHz 35
P0.4 AD4

Pin 9 is the master reset for 18

P0.3
P0.2
36
37
AD3
AD2
XTAL2
the 8051 30pF P0.1
P0.0
38
39
AD1
AD0

 When RST =1 ( least two P1.7

8

machine cycles), register 29 7

PSEN P1.6
6
P1.5

=00H
5
30 P1.4
ALE 4
P1.3
31 EA 3
P1.2
P0, P1,P2, P3 = FFH (logic 1) 9
P1.1
P1.0
2
1
RST

SP=07H 28
P2.7 AD15
5V 17
PC=0000H RD
WR
16
P3.7
P3.6
P2.6
27
26
AD14

10µF T0
15 P3.5
P2.5
P2.4
25
AD13
AD12
8051 T1
14 P3.4
P2.3
24 AD11
100Ω INT1
13 P3.3 P2.2
23
AD10
RST INT0
12
P3.2 P2.1
22 AD9
11
TXD P3.1 P2.0 21 AD8
RXD 10 P3.0
VSS

8.2kΩ 20
 Pins 40
VCC 32
30pF P0.7 AD7
19
XTAL1 33
P0.6 AD6
34
P0.5 AD5
12MHz 35
P0.4 AD4
Vcc 18
P0.3
P0.2
36
37
AD3
AD2
XTAL2
 Volt supply for 8051 30pF P0.1
38
39
AD1
P0.0 AD0
+5V 8
P1.7
Pin 40 29 PSEN P1.6
7
6
P1.5

GND: Ground, pin 20 30

ALE
P1.4
P1.3
5
4
31 EA 3
P1.2
2
P1.1
1
9 RST P1.0

28 AD15
P2.7
17 P3.7 27
RD P2.6 AD14
16 P3.6
WR 26
P2.5 AD13
15 P3.5 25
T0 P2.4 AD12
14 P3.4
T1 24
P2.3 AD11
13 P3.3 23
INT1 P2.2 AD10
12 22
INT0 P3.2 P2.1 AD9
11
TXD P3.1 P2.0 21 AD8
RXD 10 P3.0
VSS
20
 2.3. Memory organization
2.3.1 Internal RAM.
 Internal data memory space is divided
General purpose between internal RAM (00H – 7FH) and
RAM specical function registers (80H - FFH).
00H – 1FH: 4 register banks.
Bit addressable  Each banks has 8 register, R0 through R7.
RAM  Default these registers are at addresses
00H – 07H.
 2.3.1. Internal RAM
 Bit addressable RAM
General purpose (20H – 2FH).
RAM  The 8051 contains
128 bit addressable
Bit addressable locations, of which 128
RAM are at byte addresses.
SET 67H; set bit 67H
MOV A, 2DH; read a
byte.
Bit addressable RAM

 The idea of individually accessing bits through aoftware is a piwerful

feature of microcontrollers. Bits can be set, cleared, ANDed, Ored,…
with a single instruction.
The 8051 I/O ports are bit addressable.
Example: to set bit 7FH, the followin instruction:
Microcontrollers::
SETB 7FH
Microprocessors: (bit address 67H is bit at “byte address 2CH”)
MOV A,2FH ; read entire byte
ORL A,#10000000B; set bit
MOV 2FH, A; write back entire byte
 General purpose RAM 7F

General purpose RAM

 30H – 7FH
80 byte
RAM can be accessed freely 30
using the direct or indirect 2F 7F 7E 7D 7C 7B 7A 79 78
addressing modes. 2E 77 76 75 74 73 72 71 70

Example: 2D 6F 6E 6D 6C 6B 6A 69 68

- MOV A, 30H ; move a byte of data Bit addressable .

(address 5FH) to A accumulator.
- MOV R1, #30H; move 30H into 22 17 16 15 14 13 12 11 10

register R1 21 0F 0E 0D 0C 0B 0A 09 08

- MOV A, @R1 ;move the data 20 07 06 05 04 03 02 01 00

1F Bank 3
“pointed at by R1” into the Bank 2
32 byte
accumulator. Bank 1
Bank 0
00
 2.3.2 Extenal memory
 8051 architecture provides external:
+ 64K Code memory space (ROM)
+ 64K data memory space (RAM)
 Accessing external code memory
2.3.2. External memory
2.4. Special function registers (SFR)

I/O port SFRs

Control SFRs
Other SFRs
 Program status word (PSW)
Thanh ghi PSW

C (CY) PSW.7 Carry flag

AC PSW.6 Auxillary carry flag
F0 PSW.5 Flag 0
RS1 PSW.4 Register bank select 1
RS0 PSW.3 Register bank select 0
OV PSW.2 Overflow flag
-- PSW.1 Reserved
P PSW.0 Even parity flag
Program status word (PSW)

C (Carry flag)
 set if there is a carry out of bit 7 during an add or ser if there is a
borrow into bit 7 during a subtract.
MOV A,#FFH
ADD A,#1 : A=100H
 Carry flag is serving as a 1-bit register for Boolean instructions
operating on bits.
ANL C,25H
Program status word (PSW)

AC (Auxiliary carry)

 AC is set if a carry wa genereated out of bit 3 into bit 4
RS1, RS0 – Register bank select bits
Determine the active register bank.
 They are cleared after a system reset.
Program status word (PSW)

OV (over flag)
OV is set after an addition or subtraction operation if there was
arithmetic overflow. When a signed numbers are added or
subtracted, software can examine this bit to determine if the result
is in the proper range.
 When unsigned numbers are added, the OV bit can be ignored.
 Resutt greater than + 127 or less than – 128 will set the OV bit.

8EH represents -116, which is clearly not the correct result of 142, OV bit is set.
Program status word (PSW)

P (Parity bit)
 Establish even parity with the accumulator.
 The number of 1-bits in the accumulator plus the P bit is always
even.
 P bit is used in conjunction with serial port routines to include a
parity bit before transmission or to check for parity after reception.
Example:
MOV A,#10101101B
→P=1
Program status word (PSW)
B register

B register is used with the accumulator for multiply and divide

operations.
MUL A,B ; multiplies the 8 –bit unsigned values in A and B
and leaves 16-bit result in A (low-byte) and B (high byte).
DIV AB ; divided A by B, leaving the integer result in A and
the remainder in B.
B register is bit – addressable (0F0H to 0F7H)
Stack pointer (SP)

 SP contains the address of the data item currently on the top of

the stack.
 “pushing” data on the stack ( increments the SP) and “poping”
data off the stack (decrements the SP)
 The stack beginning at 60H:
MOV SP,#5FH
 Limit the stack to 32 bytes, since the uppermost address of on –chip
RAM is 7FH.
5FH is used, since the SP increments to 60H before the first push
operation.
Stack pointer (SP)

PUSH & POP instructions to temporarily store and retrieve data

ACALL , LCALL, RET, RETI instructions to save and restore the
program counter.
 Stack pointer (SP)
Example::
MOV R6,#25H
MOV R1,#12H
MOV R4,#0F3H
PUSH 6
PUSH 1
PUSH 4
Data pointer (DPTR)

DPTR used to access external code or data memory.

A 16 – bit register at addresses 82H and 83H
Example:
Port registers

 All ports are bit – addressable

Example: (A motor is connected to Port 1 bit 7)
SETB P1.0
CLR P1.0
 Check a device is busy and ready
WAIT: JB P1.5, WAIT
Timer registers

8051 contains 2 16-bits timer/counters

 Timer operation is set by the timer mode register (TMOD) and
the timer counter register (TCON)
Serial Port registers

8051 contains an on-chip serial port for communicating with serial

devices.
SBUF (Serial Data Buffer): Transmit data and receive data
SCON (Serial Port Control Register):choose the modes of
operation
Interrupt registers

IE : Interrup enable register at address 0A8H

IP : Interrupt Priority register at address 0B8H
2.5 Reset operation

 Manual reset circuit.

Register values after system reset

Registers Contents

PC 0000H
A 00H
B 00H
PSW 00H
SP 07H
DPTR 0000H
P0, P1, P2, P3 FFH

RAM is not affected by a reset operation.