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Kuliah - 12 - Basic Processing

The document describes the basic components and operation of a central processing unit (CPU). It discusses the program counter, instruction register, memory address register, memory data register, and how they work together to fetch and execute instructions. It explains the fetch, decode, and execute phases of instruction execution. It also covers different addressing modes, performing arithmetic/logic operations, and control sequences for different instruction types like addition and branches.

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9 views

Kuliah - 12 - Basic Processing

The document describes the basic components and operation of a central processing unit (CPU). It discusses the program counter, instruction register, memory address register, memory data register, and how they work together to fetch and execute instructions. It explains the fetch, decode, and execute phases of instruction execution. It also covers different addressing modes, performing arithmetic/logic operations, and control sequences for different instruction types like addition and branches.

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Central Processing Unit

Pertemuan 12
Prerequisites
What is?
Basic Operational Concept
Program Counter (PC=penunjuk ke alamat memori tertentu)
Central Processing Unit (CPU)
Instruction Register (IR=penyimpan instruksi yang sedang
dieksekusi)
Memory Address Register (MAR=penyimpan alamat memori)
Memory Data Register (MDR=penyimpan isi data dari alamat
memori)
Fundamental Concepts
Processor fetches one instruction at a time and
perform the operation specified.
Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
Instruction Register (IR)
Executing an Instruction
Fetch the contents of the memory location pointed to
by the PC. The contents of this location are loaded
into the IR (fetch phase).
IR ← [[PC]]
Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
Carry out the actions specified by the instruction in
the IR (execution phase).
Single Bus Architecture

Fig:refer from Carl Hamacher page 413


Execution of Instruction

Fetch the contents of a given memory location and


load them into a processor register.
Transfer a word of data from one processor register to
another or to the ALU.
Perform an arithmetic or a logic operation and store
the result in a processor register.
Store a word of data from a processor register into a
given memory location.
Internal processor
bus

Register Transfers Ri
Riin

Riout

Yin

Constant 4

Select MUX

A B
ALU

Zin

Z out

Fig:refer
Fig.:Input and output gating for the registersfrom Carl
Hamacher page 416
Performing an Arithmetic or Logic
Operation
 ALU gets the two operands from MUX and bus. The
result is temporarily stored in register Z.
 First operand is always send to Register Y and
Second is directly send to point B of ALU
 What is the sequence of operations to add the
contents of register R2 to those of R3 and store the
result in R4?
1. R2out, Yin
2. R3out, SelectY, Add, Zin
3. Zout, R4in
Execution of a Complete
Instruction
Add (R1), R2
Fetch the instruction(Instruction Fetch Phase)
Fetch the first operand (the contents of the memory
location Stored at R1)
Perform the addition
Load the result into R2
Execution of a Complete
Instruction
Add (R3), R1
Execution of Branch Instructions
A branch instruction replaces the contents of PC with
the branch target address, which is usually obtained
by adding an offset X given in the branch instruction.
The offset X is usually the difference between the
branch target address and the address immediately
following the branch instruction.
Conditional branch
Execution of Branch Instructions
Step Action

1 PCout , MAR in , Read, Select4, Add, Z in


2 Zout , PC in , Yin , WMF C
3 MDR out , IR in
4 Offset-field-of-IRout , Add, Z in
5 Z out , PCin , End

Figure Control sequence for an unconditional


branch instruction.
Bus A Bus B
Multiple-Bus Organization Bus C

Incrementer

 Add R1, R2, R3


PC

Re gister
file

Constant 4
Step Action
MUX

ALU R
1 PCout , R=B, MAR in , Read, IncPC
B

2 WMFC
Instruction
decoder
3 MDR outB , R=B, IR in
IR
4 R1 outA , R2 outB , SelectA, Add, R3 in , End
MDR

MAR
Figure:Control sequence for the instruction. Add
Memory bus Address
R1,R2,R3, for the three-bus organization
data lines lines

Fig:refer from Carl


Fig:Three Bus Organization of the datapath.
Hamacher page 424
Pelajari
Mode addressing : mode pengalamatan
Immediate, Indirect, Index, etc….
Phase Pengambilan instruksi (instruction fetch)
Phase Eksekusi Instruksi (Execution Fetch)
Ini masih dalam bentuk RISC (reduce instruction set
computer)
Buku referensi : Computer Organization, oleh:
Hamacher. Edisi ke 5 atau 6
Soal
Control sequence untuk (IF, EF)
1. ADD R2,R3
2. ADD (R5), R4
3. ADD R3, (R6)
Boleh tulis tangan, boleh word
Jumat, 25 Desember 2020 jam 23.59
Folder pengumpulan tugas menyusul

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