Computer Organization and Assembly Language

(CS2523)

Week 2

Department of Computer Science

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A Top-Level View of
Computer
Function and
Interconnection
Chapter 3. Computer Organization and Architecture

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Making Computer-First Approach
• If there is a particular computation to be
performed, a configuration of logic components
designed specifically for that computation could be
constructed.
• We can think of the process of connecting the
various components in the desired configuration as
a form of programming.
• The resulting “program” is in the form of hardware
and is termed a hardwired program.
• Not a flexible solution.
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Example: Full Adder Circuit
Using Logic Gates

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Making Computer- Alternate
Solution
• Construct a general-purpose configuration of arithmetic and
logic functions.
• Will perform various functions on data depending on control signals
applied to the hardware.
• Accepts data and control signals and produces results.
• The programmer merely needs to supply a new set of control
signals.
• Provide a unique code for each possible set of control signals,
and add to the general-purpose hardware a segment that can
accept a code and generate control signals
• Now instead of rewiring the hardware for each new program, all
we need to do is provide a new sequence of codes (instruction).

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von Neumann architecture (IAS
Computer)
• Data and instructions are stored in a single read–
write memory.
• The contents of this memory are addressable by
location, without regard to the type of data
contained there.
• Execution occurs in a sequential fashion (unless
explicitly modified) from one instruction to the
next.

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Instruction Cycle

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Instruction Cycle
• In its simplest form, instruction processing consists of
two steps.
• The processor reads (fetches) instructions from memory one
at a time
• executes each instruction.
• Program execution consists of repeating the process of
instruction fetch and instruction execution.
• The instruction execution may involve several operations
which depend on the nature of the instruction
• The processing required for a single instruction is called
an instruction cycle.
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Program Counter (PC) and
Instruction Register (IR)
• In a typical processor, a register called the program counter
(PC) holds the address of the instruction to be fetched next.
• Unless told otherwise, the processor always increments the
PC after each instruction fetch so that it will fetch the next
instruction in sequence
• The fetched instruction is loaded into a register in the
processor known as the instruction register (IR).
• The instruction contains bits that specify the action the
processor is to take.
• The processor interprets the instruction and performs the
required action.

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General Instruction Categories
• The required actions generally fall into four
categories
• Data may be transferred from processor to memory or
from memory to processor.
• Data may be transferred to or from a peripheral device
by transferring between the processor and an I/O
module.
• The processor may perform some arithmetic or logic
operation on data.
• An instruction may specify that the sequence of
execution be altered.

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Example
• The processor contains a single data register, called
an accumulator (AC).
• Both instructions and data are 16 bits long. Thus, it
is convenient to organize memory using 16-bit
words.
• The instruction format provides 4 bits for the
opcode, so that there can be as many as 2^4 = 16
different opcodes, and up to 2^12 = 4096 (4K)
words of memory can be directly addressed.

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Example Program Execution
• The PC contains 300, the address of the first instruction. This
instruction (the value 1940 in hexadecimal) is loaded into the
instruction register IR, and the PC is incremented.
• The first 4 bits (first hexadecimal digit) in the IR indicate that the AC
is to be loaded. The remaining 12 bits (three hexadecimal digits)
specify the address (940) from which data are to be loaded.
• The next instruction (5941) is fetched from location 301, and the PC
is incremented.
• The old contents of the AC and the contents of location 941 are
added, and the result is stored in the AC.
• The next instruction (2941) is fetched from location 302, and the PC
is incremented.
• The contents of the AC are stored in location 941.

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Description
• Instruction address calculation (iac): Determine the address of the next
instruction to be executed. Usually, this involves adding a fixed number to
the address of the previous instruction.
• For example, if each instruction is 16 bits long and memory is organized into 16-bit
words, then add 1 to the previous address.
• Instruction fetch (if): Read instruction from its memory location into the
processor.
• Instruction operation decoding (iod): Analyze instruction to determine type
of operation to be performed and operand(s) to be used.
• Operand address calculation (oac): If the operation involves reference to an
operand in memory or available via I/O, then determine the address of the
operand.
• Operand fetch (of): Fetch the operand from memory or read it in from I/O.
• Data operation (do): Perform the operation indicated in the instruction.
• Operand store (os): Write the result into memory or out to I/O.
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Effect of Clock Speed
• Fetching an instruction, decoding the instruction, performing an
arithmetic operation, and so on, are governed by a system clock.
• Typically, all operations begin with the pulse of the clock. Hence the
speed of a processor is dictated by the pulse frequency produced by the
clock, measured in cycles per second, or Hertz (Hz). For example, a 1-
GHz processor receives 1 billion pulses per second. The time between
pulses is the cycle time.
• The clock rate must be appropriate for the physical layout of the
processor. When a signal is placed on a line inside the processor, it takes
some finite amount of time for the voltage levels to settle down so that
an accurate value (logical 1 or 0) is available.
• Most instructions on most processors require multiple clock cycles to
complete. Some instructions may take only a few cycles, while others
require dozens.

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Example

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Instruction Pipelining
• An instruction pipeline reads instruction from the memory
while previous instructions are being executed in other
segments of the pipeline. Thus we can execute multiple
instructions simultaneously.

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Interrupts
• Interrupts are provided primarily as a way to
improve processing efficiency as most external
devices are much slower than the processor.
• If the processor is transferring data to a printer,
after each write operation, the processor must
pause and remain idle until the printer catches up.
• The length of this pause may be on the order of
many thousands of instruction cycles.
• Clearly, this is a very wasteful use of the processor.

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Description
• The user program performs a series of WRITE calls interleaved
with processing.
• The WRITE calls are to an I/O program that will perform the actual
I/O operation.
• The I/O program consists of three sections:
• A sequence of instructions, (labeled 4) to prepare for the actual I/O
operation.
• The actual I/O command. Once this command is issued, the program
must wait for the I/O device to perform the requested function.
• A sequence of instructions, labeled 5 in the figure, to complete the
operation.
• Because the I/O operation may take a relatively long time to
complete, the I/O program is hung up waiting for the operation to
complete.
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Interrupts and the instruction
cycle
• With interrupts, the processor can be engaged in executing other instructions
while an I/O operation is in progress.
• As before, the user program reaches a point at which it makes a system call in
the form of a WRITE call.
• The I/O program that is invoked in this case consists only of the preparation
code and the actual I/O command. After these few instructions have been
executed, control returns to the user program.
• Meanwhile, the external device is busy accepting data from computer
memory and printing it.
• Once finished, the I/O module for that external device sends an interrupt
request signal to the processor.
• The processor responds by suspending operation of the current program,
branching off to a program to service that particular I/O device, known as an
interrupt handler, and resuming the original execution after the device is
serviced.
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• The processor and the operating system are
responsible for suspending the user program and
then resuming it at the same point.
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Assembly and Machine
Language

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Assembly and Machine Language
• Machine language
• Native to a processor: executed directly by hardware
• Instructions consist of binary code: 1s and 0s
• Assembly language
• Slightly higher-level language
• Readability of instructions is better than machine
language
• One-to-one correspondence with machine language
instructions

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Compiler and Assembler
Advantages of High-Level
Languages
• Program development is faster
• High-level statements: fewer instructions to code
• Program maintenance is easier
• Programs are portable
• Contain few machine-dependent details
• Can be used with little or no modifications on different
machines
• Compiler translates to the target machine language

• Assembly language programs are not portable

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Programmer’s View of a
Computer System

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Increased level Application Programs
of abstraction High-Level Language Level 5

Assembly Language Level 4

Operating System
Level 3

Instruction Set
Architecture Level 2

Microarchitecture Level 1
Each level
Digital Logic hides the
Level 0 details of the
level below it
Description
• Application Programs (Level 5)
• Written in high-level languages (Java, C++). compiled into assembly language
level (Level 4)
• Assembly Language (Level 4)
• Instruction mnemonics are used which have one-to-one correspondence to
machine language. Calls functions written at the operating system level (Level 3)
• Operating System (Level 3)
• Provides services to level 4 and 5 programs
• Translated to run at the machine instruction level (Level 2)
• Instruction Set Architecture (Level 2)
• Machine instructions, registers, and memory are exposed
• Microarchitecture (Level 1)
• Controls the execution of machine instructions (Level 2)
• Digital Logic (Level 0)
• Implements the microarchitecture using digital logic gates

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