3130704

Digital Fundamentals

Module 1:
Fundamentals of Digital
Systems and Logic families
 Topics to be covered
 Logic Gates
 Boolean Algebra
 Number Systems
 Codes
 Logic Family Terminology

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Introduction: Digital
Digital Fundamentals
Fundamentals 22
 Logic Gates
 Most basic logical unit of the digital system is gate circuit
 Types of gate circuits are as follows
1. AND Gate
2. OR Gate
3. NOT Gate (Inverter)
4. NOR Gate
5. NAND Gate
6. XOR Gate
7. XNOR Gate

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Digital Fundamentals
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 1. AND Gate
 AND Gate has an output which is normally at logic level “0” and
only goes “HIGH” to a logic level “1” when ALL of its inputs are at
logic level “1”
2-input AND Gate Logic Notation
A
C 𝐶 = 𝐴∙ 𝐵
B
Truth Table
A B C
0 0 0
0 1 0
1 0 0
1 1 1
Introduction:
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Digital Fundamentals
Fundamentals 44
 2. OR Gate
 OR Gate or Inclusive-OR gate has an output which is normally at
logic level “0” and only goes “HIGH” to a logic level “1” when one
or more of its inputs are at logic level “1”.
2-input OR Gate Logic Notation
A
C 𝐶 = 𝐴+ 𝐵
B
Truth Table
A B C
0 0 0
0 1 1
1 0 1
1 1 1
Introduction:
Introduction: Digital
Digital Fundamentals
Fundamentals 55
 3. NOT (Inverter) Gate
 NOT gate has an output which is always opposite to input level.

Inverter Gate Logic Notation

A C 𝐶= 𝐴𝑜𝑟 𝐶= 𝐴′
Truth Table
A C
0 1
1 0

Introduction:
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Digital Fundamentals
Fundamentals 66
 4. NOR Gate
 NOR Gate is an OR gate followed by an inverter.

2-input NOR Gate Logic Notation

A 𝐶 =( 𝐴+ 𝐵 )
′

B C
Truth Table
A B C
0 0 1
0 1 0
1 0 0
1 1 0

Introduction:
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Digital Fundamentals
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 5. NAND Gate
 NAND Gate is an AND gate followed by an inverter.

2-input NAND Gate Logic Notation

A 𝐶 =( 𝐴 ∙ 𝐵)′
B C
Truth Table
A B C
0 0 1
0 1 1
1 0 1
1 1 0

Introduction:
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Digital Fundamentals
Fundamentals 88
 6. Exclusive-OR (X-OR) Gate
 X-OR gate that has 1 state when one and only one of its two inputs
assumes a logic 1 state and has 0 state when all of its input are
same.
 Also known as anti-coincidence gate or inequality detector.
2-input XOR Gate Logic Notation
A
C 𝐶= 𝐴 𝐵
B Truth Table
A B C
0 0 0
0 1 1
1 0 1
1 1 0
Introduction:
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Digital Fundamentals
Fundamentals 99
 7. Exclusive-NOR (X-NOR) Gate
 X-NOR gate that has 1 state when all of its input are same and has
0 state when one of its input has 0 state and other input is 1 state.
 Also known as equality detector.

2-input XNOR Gate Logic Notation

A
C 𝐶= 𝐴 𝐵
B Truth Table
A B C
0 0 1
0 1 0
1 0 0
1 1 1
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Digital Fundamentals
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10
 NAND as Universal Gate
(AB)’ ((AB)’)’ = AB
A
A A’
B
NOT using NAND AND using NAND

A’
A
(A’B’)’ = (A+B)
B
B’
OR using NAND

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Digital Fundamentals
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11
 NOR as Universal Gate
(A+B)’ ((A+B)’)’ = A+B
A
A A’
B
NOT using NOR OR using NOR

A’
A
(A’+B’)’ = AB
B
B’
AND using NOR

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Digital Fundamentals
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 Boolean Algebra
 AND laws  OR laws

 Commutative laws ``

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Digital Fundamentals
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 Boolean Algebra
 Distributive laws  Redundant Literal Rule

 Idempotent laws  Absorption laws

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Digital Fundamentals
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 Boolean Algebra
 De Morgan’s Theorem

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 Boolean Algebra
 De Morgan’s Theorem

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 Boolean Algebra
 De Morgan’s Theorem

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 Reducing Boolean Expression
 Reduce the expression

𝑓 = 𝐴+ 𝐵[ 𝐴𝐶+ ( 𝐵+ 𝐶 ) 𝐷]
𝑓 = 𝐴+ 𝐵[ 𝐴𝐶+𝐵𝐷+𝐶 𝐷 ] (Distributive law)
𝑓 = 𝐴+ 𝐵𝐴𝐶+𝐵𝐵𝐷+ 𝐵 𝐶 𝐷 (Distributive law)
𝑓 = 𝐴+ 𝐴𝐵𝐶+𝐵𝐷+𝐵 𝐶 𝐷 (A.A = A)
𝑓 = 𝐴(1+ 𝐵𝐶)+ 𝐵𝐷(1+ 𝐶)
𝑓 = 𝐴+ 𝐵𝐷 (1 + A = 1)

Introduction:
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 Reducing Boolean Expression
 Reduce the expression

𝑓 = 𝐴[𝐵+𝐶( 𝐴𝐵+ 𝐴𝐶)]

𝑓 = 𝐴[𝐵+𝐶( 𝐴𝐵 𝐴 𝐶)] (DeMorgan’s law)
𝑓 = 𝐴[𝐵+𝐶 ( 𝐴+𝐵)( 𝐴+𝐶 )] (DeMorgan’s law)
𝑓 = 𝐴[𝐵+𝐶( 𝐴 𝐴+ 𝐴 𝐶+𝐵 𝐴+ 𝐵 𝐶)] (Distributive law)
𝑓 = 𝐴[𝐵+𝐶 𝐴+𝐶 𝐴 𝐶+𝐶 𝐵 𝐴+𝐶 𝐵 𝐶] (Distributive law)
𝑓 = 𝐴[𝐵+𝐶 𝐴+0+𝐶 𝐵 𝐴+0] (A.A’ = 0)
𝑓 = 𝐴𝐵+ 𝐴 𝐶 𝐴+ 𝐴𝐶 𝐵 𝐴 (Distributive law)
𝑓 = 𝐴𝐵+ 0+0 (A.A’ = 0)
𝑓 = 𝐴𝐵
Introduction:
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Digital Fundamentals
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 Exercise
𝑓 =0
𝑓 =𝐵
1. Show that

Introduction:
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 Number
Systems

Unit
Unit –– 1:
1: Binary
Binary Systems
Systems &
& Logic
Logic Circuits
Circuits Darshan
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
 Common Number Systems
System Base Symbols Used by Used in
Humans? Computers?
Decimal 10 0, 1, … 9 Yes No
Binary 2 0, 1 No Yes
Octal 8 0, 1, … 7 No No
Hexa- 16 0, 1, … 9, No No
decimal A, B, … F

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 Quantities / Counting
Hexa- Hexa-
Decimal Binary Octal decimal Decimal Binary Octal decimal
0 0 0 0 8 1000 10 8
1 1 1 1 9 1001 11 9
2 10 2 2 10 1010 12 A
3 11 3 3 11 1011 13 B
4 100 4 4 12 1100 14 C
5 101 5 5 13 1101 15 D
6 110 6 6 14 1110 16 E
7 111 7 7 15 1111 17 F

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 Conversion among Bases
 Possibilities

Decimal Octal

Binary Hexadecimal

 Example

2510 = 110012 = 318 = 1916 Base

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Digital Fundamentals
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 Decimal to Binary
Decimal Binary

 Technique
• Divide by two, keep track of the remainder
• First remainder is bit 0 (LSB, least-significant bit)
• Second remainder is bit 1 and so on

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 Example (Decimal to Binary)

12510 = ?2 2 125 1
2 62 0
2 31 1
2 15 1
2 7 1
2 3 1
2 1 1
0
12510 = 11111012

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 Example (Decimal to Binary)

0.687510 = ?2
integer fraction
0.6875 x 2 = 1.3750 1 + 0.3750
0.3750 x 2 = 0.7500 0 + 0.7500
0.7500 x 2 = 1.5000 1 + 0.5000
0.5000 x 2 = 1.0000 1 + 0.0000

0.687510 = 0.10112

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 Exercise
 (32)10 = ( )2
 (555)10 = ( )2
 (12999)10 = ( )2
 (157.63)10 = ( )2
 (64.125)10 = ( )2

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 Binary to Decimal
Binary Decimal

 Technique
• Multiply each bit by 2n, where n is the “weight” of the bit
• The weight is the position of the bit, starting from 0 on the right
• Add the results

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 Example (Binary to Decimal)

1 0 1 0 1 1

1 x 25 + 0 x 24 + 1 x 23 + 0 x 22 + 1 x 21 + 1 x 20
32 + 0 + 8 + 0 + 2 + 1
4310

1010112 = 4310

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 Example (Binary to Decimal)

1 1 . 1 1

1 x 21 + 1 x 20 + 1 x 2-1 + 1 x 2-2
2 + 1 + 0.5 + 0.25
3.7510

11.112 = 3.7510

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 Exercise
 (11011)2 = ( )10
 (101101)2 = ( )10
 (11101111)2 = ( )10
 (110.011)2 = ( )10
 (1001.0010)2 = ( )10

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Digital Fundamentals
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 Decimal to Octal
Decimal Octal

 Technique
• Divide by eight
• Keep track of the remainder

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Digital Fundamentals
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 Example (Decimal to Octal)

12510 = ?8 8 125 5
8 15 7
8 1 1
0

12510 = 1758

Introduction:
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Digital Fundamentals
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 Example (Decimal to Octal)

0.687510 = ?8
integer fraction
0.6875 x 8 = 5.5000 5 + 0.5000
0.5000 x 8 = 4.0000 4 + 0.0000

0.687510 = 0.548

Introduction:
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Digital Fundamentals
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 Exercise
 (32)10 = ( )8
 (555)10 = ( )8
 (12999)10 = ( )8
 (157.63)10 = ( )8
 (64.125)10 = ( )8

Introduction:
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Digital Fundamentals
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 Octal to Decimal
Octal Decimal

 Technique
• Multiply each bit by 8n, where n is the “weight” of the bit
• The weight is the position of the bit, starting from 0 on the right
• Add the results

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Digital Fundamentals
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 Example (Octal to Decimal)

7 2 4

7 x 82 + 2 x 81 + 4 x 80
448 + 16 + 4

46810

7248 = 46810

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Digital Fundamentals
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 Example (Octal to Decimal)

4 3 . 2 5

4 x 81 + 3 x 80 + 2 x 8-1 + 5 x 8-2
32 + 3 + 0.25 + 0.0781
35.328110

43.258 = 35.328110

Introduction:
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Digital Fundamentals
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 Exercise
 (32)8 = ( )10
 (555)8 = ( )10
 (12333)8 = ( )10
 (157.63)8 = ( )10
 (64.125)8 = ( )10

Introduction:
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Digital Fundamentals
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 Decimal to Hexa-Decimal
Decimal Hexa-Decimal

 Technique
• Divide by 16
• Keep track of the remainder

Introduction:
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Digital Fundamentals
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 Example (Decimal to HexaDecimal)

123410 = ?16 16 1234 2

16 77 13=D
16 4 4
0

123410 = 4D216

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Digital Fundamentals
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 Exercise
 (32)10 = ( )16
 (555)10 = ( )16
 (12999)10 = ( )16
 (157.63)10 = ( )16
 (64.125)10 = ( )16

Introduction:
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Digital Fundamentals
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 Hexa-Decimal to Decimal
Hexa-Decimal Decimal

 Technique
• Multiply each bit by 16n, where n is the “weight” of the bit
• The weight is the position of the bit, starting from 0 on the right
• Add the results

Introduction:
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Digital Fundamentals
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 Example (HexaDecimal to Decimal)

A B C

A x 162 + B x 161 + C x 160

10 x 162 + 11 x 161 + 12 x 160
2560 + 176 + 12
274810
ABC16 = 274810

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Digital Fundamentals
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 Exercise
 (FA8)16 = ( )10
 (9AC3)16 = ( )10
 (1A74D)16 = ( )10
 (1AC.9A)16 = ( )10
 (ABC.5AC)16 = ( )10

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Digital Fundamentals
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 Octal to Binary
Octal Binary

 Technique
• Convert each octal digit to a 3-bit equivalent binary representation

Introduction:
Introduction: Digital
Digital Fundamentals
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47
 Octal - Binary Table
Octal Binary
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

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Digital Fundamentals
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 Example (Octal to Binary)

7058 = ?2

7 0 5

111 000 101

7058 = 1110001012

Introduction:
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Digital Fundamentals
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 Exercise
 (463)8 = ( )2
 (2056)8 = ( )2
 (2057.64)8 = ( )2
 (6543.04)8 = ( )2
 (7476.47)8 = ( )2

Introduction:
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Digital Fundamentals
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50
 Binary to Octal
Binary Octal

 Technique
• Group bits in threes, starting on right
• Convert to octal digits

Introduction:
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Digital Fundamentals
Fundamentals 51
51
 Example (Binary to Octal)

10110101112 = ?8

001 011 010 111

1 3 2 7

10110101112 = 13278

Introduction:
Introduction: Digital
Digital Fundamentals
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 Exercise
 (11011)2 = ( )8
 (101101)2 = ( )8
 (11101111)2 = ( )8
 (110.011)2 = ( )8
 (1001.0010)2 = ( )8

Introduction:
Introduction: Digital
Digital Fundamentals
Fundamentals 53
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 Hexa-Decimal to Binary
Hexa-Decimal Binary

 Technique
• Convert each hexadecimal digit to a 4-bit equivalent binary representation

Introduction:
Introduction: Digital
Digital Fundamentals
Fundamentals 54
54
 Hexa-Decimal to Binary
Hexa- Binary Hexa- Binary
Decimal Decimal
0 0000 8 1000
1 0001 9 1001
2 0010 A 1010
3 0011 B 1011
4 0100 C 1100
5 0101 D 1101
6 0110 E 1110
7 0111 F 1111

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Digital Fundamentals
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 Example (Hexa-Decimal to Binary)

10AF16 = ?2

1 0 A F

0001 0000 1010 1111

10AF16 = 10000101011112

Introduction:
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Digital Fundamentals
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 Exercise
 (FA8)16 = ( )2
 (9AC3)16 = ( )2
 (1A74D)16 = ( )2
 (1AC.9A)16 = ( )2
 (ABC.5AC)16 = ( )2

Introduction:
Introduction: Digital
Digital Fundamentals
Fundamentals 57
57
 Binary to Hexa-Decimal
Binary Hexa-Decimal

 Technique
• Group bits in fours, starting on right
• Convert to hexadecimal digits

Introduction:
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Digital Fundamentals
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 Example (Binary to Hexa-Decimal)

10110101112 = ?16

0010 1101 0111

2 D 7

10110101112 = 2D716

Introduction:
Introduction: Digital
Digital Fundamentals
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 Exercise
 (11011)2 = ( )16
 (101101)2 = ( )16
 (11101111)2 = ( )16
 (110.011)2 = ( )16
 (1001.0010)2 = ( )16

Introduction:
Introduction: Digital
Digital Fundamentals
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 Octal to Hexa-Decimal
Octal Hexa-Decimal

 Technique
• Convert Octal to Binary
• Regroup bits in fours from right
• Convert Binary to Hexa-Decimal

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Digital Fundamentals
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 Example (Octal to Hexa-Decimal)

10768 = ?16

1 0 7 6

001 000 111 110

0010 0011 1110

2 3 E

10768 = 23E16
Introduction:
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Digital Fundamentals
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 Exercise
 (463)8 = ( )16
 (2056)8 = ( )16
 (2057.64)8 = ( )16
 (6543.04)8 = ( )16
 (7476.47)8 = ( )16

Introduction:
Introduction: Digital
Digital Fundamentals
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63
 Hexa-Decimal to Octal
Hexa-Decimal Octal

 Technique
• Convert Hexa-Decimal to Binary
• Regroup bits in three from right
• Convert Binary to Octal

Introduction:
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Digital Fundamentals
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 Example (Hexa-Decimal to Octal)

1F0C16 = ?8

1 F 0 C

0001 1111 0000 1100

000 001 111 100 001 100

0 1 7 4 1 4

1F0C16 = 174148
Introduction:
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Digital Fundamentals
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 Exercise
 (FA8)16 = ( )8
 (9AC3)16 = ( )8
 (1A74D)16 = ( )8
 (1AC.9A)16 = ( )8
 (ABC.5AC)16 = ( )8

Introduction:
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Digital Fundamentals
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 Signed Binary Numbers
 Two ways of representing signed numbers:
 1) Sign-magnitude form, 2) Complement form.
 Most of computers use complement form for negative number
notation.
 1’s complement and 2’s complement are two different methods in
this type.

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 1’s Complement
 1’s complement of a binary number is obtained by subtracting
each digit of that binary number from 1.
 Example

1 1 1 1 1 1 1 . 1 1
- 1 1 0 1 - 1 0 1 . 0 1
0 0 1 0 0 1 0 . 1 0
(1’s complement of 1101) (1’s complement of 101.01)

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 2’s Complement
 2’s complement of a binary number is obtained by adding 1 to its
1’s complement.
 Example

1 1 1 1 1 1 1 . 1 1
- 1 1 0 0 - 1 0 1 . 0 1
0 0 1 1 0 1 0 . 1 0
+ 1 + 1
0 1 0 0 0 1 0 . 1 1
(2’s complement of 1100) (2’s complement of 101.01)
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 Representation of negative number in 2’s complement
form
 Express -65.5 in 12 bit 2’s complement form.

2 65 1 0.5 x 2 = 1.0
2 32 0 So, result in 12-bit binary is as follows:
2 16 0 65.510 = 01000001.10002
2 8 0 For negative number, we have to
convert this into 2’s complement form
2 4 0
2 2 0 -65.510 = 10111110.10002
2 1 1
0

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 Exercise
 Express -45 in 8-bit 2’s complement form.
 Express -73.75 in 12 bit 2’s complement form.

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Digital Fundamentals
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 Accuracy in Binary Number Conversion
 Convert (0.252)10 to binary with an error less than 1%.
Solution
 Absolute value of allowable error is found by calculating 1% of the
number

 Maximum error due to truncation is set to be less than allowable

error by solving from . This equation is written as

 Inverting both sides of the inequality

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 Accuracy in Binary Number Conversion
 Taking log of both sides and solving for

 This indicates that the use of 9 bits in the binary number will
guarantee an error less than 1%.
 So the conversion is carried out to 9 places which results in

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 9’s Complement
 9’s complement of a decimal number is obtained by subtracting
each digit of that decimal number from 9.
 Example

9 9 9 9 9 9 9 . 9 9
- 3 4 6 5 - 7 8 2 . 5 4
6 5 3 4 2 1 7 . 4 5
(9’s complement of 3465) (9’s complement of 782.54)

Introduction:
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Digital Fundamentals
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 10’s Complement
 10’s complement of a decimal number is obtained by adding 1 to its 9’s
complement.
 Example

9 9 9 9 9 9 9 . 9 9
- 3 4 6 5 - 7 8 2 . 5 4
6 5 3 4 2 1 7 . 4 5
+ 1 + 1
6 5 3 5 2 1 7 . 4 6
(10’s complement of 3465) (10’s complement of 782.54)
Introduction:
Introduction: Digital
Digital Fundamentals
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 Subtraction using 9’s complement
 Obtain 9’s complement of subtrahend
 Add the result to minuend and call it intermediate result
 If carry is generated then answer is positive and add the carry to
Least Significant Digit (LSD)
 If there is no carry then answer is negative and take 9’s
complement of intermediate result and place negative sign to the
result.

Introduction:
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Digital Fundamentals
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 Example
1) 745.81 – 436.62

7 4 5 . 8 1 7 4 5 . 8 1
9’s complement
- 4 3 6 . 6 2 + 5 6 3 . 3 7
3 0 9 . 1 9 1 3 0 9 . 1 8
+ 1
3 0 9 . 1 9

Introduction:
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Digital Fundamentals
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 Example
2) 436.62 - 745.81

4 3 6 . 6 2 4 3 6 . 6 2
9’s complement
- 7 4 5 . 8 1 + 2 5 4 . 1 8
- 3 0 9 . 1 9 6 9 0 . 8 0
9’s complement

- 3 0 9 . 1 9
As carry is not generated, so take 9’s
complement of the intermediate
result and add ‘ – ‘ sign to the result

Introduction:
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Digital Fundamentals
Fundamentals 78
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 Subtraction using 10’s complement
 Obtain 10’s complement of subtrahend
 Add the result to minuend
 If carry is generated then ignore it and result itself is answer
 If there is no carry then answer is negative and take 10’s
complement of result and place negative sign to the result.

Introduction:
Introduction: Digital
Digital Fundamentals
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 Example
1) 745.81 – 436.62

7 4 5 . 8 1 7 4 5 . 8 1
10’s complement
- 4 3 6 . 6 2 + 5 6 3 . 3 8
3 0 9 . 1 9 1 3 0 9 . 1 9

Ignore the carry

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 Example
2) 436.62 - 745.81

4 3 6 . 6 2 4 3 6 . 6 2
10’s complement
- 7 4 5 . 8 1 + 2 5 4 . 1 9
- 3 0 9 . 1 9 6 9 0 . 8 1
10’s complement

- 3 0 9 . 1 9
As carry is not generated, so take
10’s complement of the intermediate
result and add ‘ – ‘ sign to the result

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 Binary Addition
 Rules for binary addition 0+0=0
0+1=1
1+0=1
1 1 1 1 1 1 1 + 1 = 10 i.e. 0
with a carry of
1 1 0 1 . 1 0 1 1
+ 0 1 1 1 . 0 1 1
1 0 1 0 1 . 0 0 0

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 Binary Subtraction
 Rules for binary subtraction 0–0=0
1–1=0
1–0=1
0 1 10 1 1 10
1 0 1 0 . 0 1 10 0 – 1 = 1, with
a borrow 1
- 0 1 1 1 . 1 1 1
0 0 1 0 . 0 1 1

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 Binary Multiplication
10111
x 10011
10111
10111
00000
00000
10111
110110101

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84
 Binary Division
110 1 0 1 1 0 1 0 111. 1
000
1 0 11
110
1010
110
1 0 01
110
110
110
000

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 Subtraction using 1’s Complement
 Obtain 1’s complement of subtrahend
 Add the result to minuend and call it intermediate result
 If carry is generated then answer is positive and add the carry to
Least Significant Digit (LSD)
 If there is no carry then answer is negative and take 1’s
complement of intermediate result and place negative sign to the
result.

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 Example
1) 68.75 – 27.50

6 8. 75 0100 0 10 0. 1 1 0 0
- 2 7. 50 1’s complement
+ 1110 0 10 0. 0 1 1 1
+ 4 1. 25 10 01 01 00 1. 0 0 1 1
+1
00 1 01 001. 0 1 0 0

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 Example
2) 43.25 - 89.75

4 3. 25 0010 1 01 1. 0 1 0 0
- 8 9. 75 1’s complement
+ 1010 0 11 0. 0 0 1 1
- 4 6. 50 1 10 10 00 1. 0 1 1 1
1’s complement

0 01 01 11 0. 1 0 0 0
As carry is not generated, so take 1’s
complement of the intermediate
result and add ‘ – ‘ sign to the result

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 Subtraction using 2’s Complement
 Obtain 2’s complement of subtrahend
 Add the result to minuend
 If carry is generated then ignore it and result itself is answer
 If there is no carry then answer is negative and take 2’s
complement of result and place negative sign to the result.

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 Example
1) 68.75 – 27.50

6 8. 75 0100 0 10 0. 1 1 0 0
- 2 7. 50 2’s complement
+ 1110 0 10 0. 1 0 0 0
+ 4 1. 25 1 0 01 01 00 1. 0 1 0 0
Ignore Carry bit
0 01 01 00 1. 0 1 0 0

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 Example
2) 43.25 - 89.75

4 3. 25 0010 1 01 1. 0 1 0 0
- 8 9. 75 2’s complement
+ 1010 0 11 0. 0 1 0 0
- 4 6. 50 1 10 10 00 1. 1 0 0 0
2’s complement

0 01 01 11 0. 1 0 0 0
As carry is not generated, so take 2’s
complement of the intermediate
result and add ‘ – ‘ sign to the result

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 Signed Number Representation
The 2’s complement system for representing signed
numbers works like this:

1) If the number is positive, the magnitude is represented in

Its true binary form and a sign bit 0 is placed in front of MSB.

2) If the number is negative, the magnitude is represented in

Its 2’s complement form and a sign bit 1 is placed in front of
MSB.

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 Signed Number Representation

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 Binary Codes

Unit
Unit –– 1:
1: Binary
Binary Systems
Systems &
& Logic
Logic Circuits
Circuits Darshan
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
 8421 BCD Code (Natural BCD Code)
 Each decimal digit, 0 through 9, is coded by 4-bit binary number
 8, 4, 2 and 1 weights are attached to each bit
 BCD code is weighted code
 1010, 1011, 1100, 1101, 1110 and 1111 are illegal codes
 Less efficient than pure binary
 Arithmetic operations are more complex than in pure binary
 Example
Decimal 1 4

BCD 0001 0100

Binary 1110
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 Binary Codes
Decimal Binary BCD Decimal Binary BCD

0 0 0000 8 1000 1000

1 1 0001 9 1001 1001
2 10 0010 10 1010 0001 0000
3 11 0011 11 1011 0001 0001
4 100 0100 12 1100 0001 0010
5 101 0101 13 1101 0001 0011
6 110 0110 14 1110 0001 0100
7 111 0111 15 1111 0001 0101

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 BCD Addition

2 5 0 0 1 0 0 1 0 1
+ 1 3 + 0 0 0 1 0 0 1 1
3 8 0 0 1 1 1 0 0 0
No carry, no illegal code. So, this is
the correct sum.

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 BCD Addition

679.6 0110 0111 1001 .0110

+ 536.8 + 0101 0011 0110 .1000
1216.4 1011 1010 1111 .1110 All are illegal codes
+0110 +0110 +0110+.0110 Add 0110 to each

10001 10000 10101 1.0100 Propagate carry

+1 +1 +1 +1
0001 0010 0001 0110 .0100 Corrected Sum

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 BCD Subtraction

3 8 0 0 1 1 1 0 0 0
- 1 5 - 0 0 0 1 0 1 0 1
2 3 0 0 1 0 0 0 1 1
No borrow. So, this is the correct
difference.

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 BCD Subtraction

206.7 0010 0000 0110 .0111

- 147.8 - 0001 0100 0111 .1000
Borrows are
58.9 0000 1011 1110 .1111 present
-0110 -0110 -.0110 Subtract 0110
Corrected
0101 1000 .1001 difference

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 Excess Three (XS-3) Code
 Excess Three Code = 8421 BCD + 0011(3)
 XS-3 code is non-weighted BCD code
 Also known as self complementing code
 0000, 0001, 0010, 1101, 1110 and 1111 are illegal codes
 Example

Decimal 1 4

BCD 0001 0100

XS-3 0100 0111

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 XS-3 Addition

3 7 0 1 1 0 1 0 1 0
+ 2 8 + 0 1 0 1 1 0 1 1
6 5 1 0 1 1 10 1 0 1
Propagate carry to next group +1
• Add 0011 to group 1 1 0 0 0 1 0 1
which generated carry
• Subtract 0011 to group - 0 0 1 1+ 0 0 1 1
which do not generated
carry 1 0 0 1 1 0 0 0

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 XS-3 Addition

247.6 0101 0111 1010 .1001

+ 359.4 + 0110 1000 1100 .0111
607.0 1011 1111101101.0000 Carry generated

• Add 0011 to +1 +1 Propagate carry

group which 1011 10000 0111 .0000

generated
carry
+1
• Subtract 0011 1100 0000 0111 .0000
to group which
do not
- 0011 +0011 +0011+.0011
generated Corrected Sum
1001 0011 1010 .0011 in XS-3
carry
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 XS-3 Subtraction

267 0101 1001 1010

- 175 - 0100 1010 1000
092 0000 1111 0010
• Subtract 0011 to
+0011 -0011 +0011
group which
0011 1100 0101 generated borrow
• Add 0011 to group
which do not
generated borrow

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 XS-3 Subtraction

57.6 1000 1010 .1001

- 27.8 - 0101 1010 .1011
29.8 0010 1111 .1110
• Subtract 0011 to
+0011 -0011 -.0011
group which
0101 1100 .1011 generated borrow
• Add 0011 to group
which do not
generated borrow

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 Gray Code
 Only one bit changes between each pair of successive code words
(Unit distance code).
 Gray code is a reflected code.
 Gray codes are designed recursively using following rules:
• 1-bit Gray code has two code words, 0 and 1.
• The first 2n code words of an (n+1)-bit Gray code equal the code words of n-
bit gray code, written in order with a leading 0 appended.
• The last 2n code words of an (n+1)-bit Gray code equal the code words of n-
bit gray code, but written in reverse order with a leading 1 appended.

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 Gray Code
Decimal 4-bit Binary
1-bit 2-bit 3-bit 4-bit
0 00 000 0000 0 0000
1 01 001 0001 1 0001
11 011 0011 2 0010
10 010 0010 3 0011
110 0110 4 0100
111 0111 5 0101
101 0101 6 0110
100 0100 7 0111
1100 8 1000
1101 9 1001
1111 10 1010
1110 11 1011
1010 12 1100
1011 13 1101
1001 14 1110
1000 15 1111
 Binary to Gray Conversion
 Conversion of n-bit Binary number (B) to Gray Code (G) is as
follows:

 Example: Convert (1001)2 to Gray Code.

Binary 1 ❑ 0 ❑ 0 ❑ 1

Gray 1 1 0 1

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 Gray to Binary Conversion
 Conversion of n-bit Gray Code (G) to Binary Number (B) is as
follows:

 Example: Convert Gray code 1101 to Binary.

Gray 1 1 0 1

❑ ❑ ❑
Binary 1 0 0 1

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 Error-Detecting Codes
 Noise can alter or distort the data in transmission.
 The 1s may get changed to 0s and 0s to 1s.
 Because digital systems must be accurate to the digit, errors can
pose a serious problem.
 Single bit error should be detect & correct by different schemes.
 Parity, Check Sums and Block Parity are the examples of error
detecting code.

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 Parity
 Parity bit is the simplest technique.
 There are two types of parity – Odd parity and Even parity.
 For odd parity, the parity is set to a 0 or a 1 at the transmitter such
that the total number of 1 bits in the word including the parity bit
is an odd number.
 For even parity, the parity is set to a 0 or a 1 at the transmitter
such that the total number of 1 bits in the word including the
parity bit is an even number.
 For example, 0110 binary number has “1” as Odd parity and “0” as
even parity.

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 Parity
 Detect a single-bit error but can not detect two or more errors
within the same word.
 In any practical system, there is always a finite probability of the
occurrence of single error.
 E.g. In an even-parity scheme, code 10111001 is erroneous
because number of 1s is odd(5), while code 11110110 is error free
because number of 1s is even(6).

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 Check Sums
 Simple parity can not detect two errors within the same word.
 Added to the sum of the previously transmitted words
 At the transmission, the check sum up to that time is sent to the
receiver.
 The receiver can check its sum with the transmitted sum.
 If the two sums are the same, then no errors were detected at the
receiver end.
 If there is an error, the receiving location can ask for
retransmission of the entire data.
 This type of transmission is used in teleprocessing system.

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 Block Parity
01011011 0 01011011 0 01011011 0
10010101 1 10010101 1 10010101 1
01101110 0 01100110 0 01101110 0
11010011 0 11010011 0 10000011 0
10001101 1 10001101 1 10001101 1
01110111 1 01110111 1 01110111 1
01110110 0 01110110 0 01110110 0
Parity Row

Parity Column

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 Error Correcting Code
 7-bit Hamming Code is widely used error correcting code,
containing 4 bits of data and 3 bits of even parity.
 Pattern: P1 P2 D3 P4 D5 D6 D7
 Group-1: P1D3D5D7, Group-2: P2D3D6D7, Group-3: P4D5D6D7

 Example: Data = 1101

P 1 P 2 D3 P 4 D5 D6 D7 = P 1 P 2 1 P 4 1 0 1
P 1 D3 D5 D7 = 1 1 1 1
P 2 D3 D6 D7 = 0 1 0 1
P 4 D5 D6 D7 = 0 1 0 1
 7-bit Hamming Code is 1 0 1 0 1 0 1

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 Error Correcting Code
 How to detect error?
 Example: Received data = 1001001
P1 P2 D3 P4 D5 D6 D7 = 1 0 0 1 0 0 1
P1 D3 D5 D7 = 1 0 0 1 (No Error)
P2 D3 D6 D7 = 0 0 0 1 (Error)
P4 D5 D6 D7 = 1 0 0 1 (No Error)
 The error word is 0 1 0 = 210.
 Complement the 2nd bit (from left).
 Correct code is 1 1 0 1 0 0 1

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 Digital IC Specification
 Threshold voltage: It is defined as that voltage at the input of a gate which
causes a change in the state of the output from one logic level to the other.
 Propagation Delay: A pulse through a gate takes a certain amount of time to
propagate from input to output. This interval of time is known as the
propagation delay of gate.
• It is the average transition delay time tpd, expressed by
• tpd = (tPLH + tPHL)/2
• where, tPLH is the signal delay time when the output goes from a logic 0 to a
logic 1 state and tPHL is the signal delay time when the output goes from a
logic 1 to logic 0 state.
 Power dissipation: The power dissipation, PD, of a logic gate is the power
required by the gate to operate with 50% duty cycle at a specified frequency
and is expressed in milliwatts.
• PD = Vcc x Icc(avg)/n, where Icc(avg) = (ICCH+ICCL)/2
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 Digital IC Specification
 Fan-in: The fan-in of a logic gate is defined as the number of inputs that the
gate is designed to handle.
 Fan-out: The fan-out (also called the loading factor) of a logic gate is defined as
the maximum number of standard loads that the output of the gate can drive
without impairing its normal operation.
 Voltage parameters:
• VIH(min): It is the minimum voltage level required at the input of a gate for
that input to be treated as a logic 1. Any voltage below this level will not be
accepted as a logic 1 input by the logic circuit.
• VOH(min): It is the minimum voltage level required at the output of a gate
for that output to be treated as a logic 1. Any voltage below this level will
not be accepted as a logic 1 output.
• VIL(max): It is the maximum voltage level that can be treated as logic 0 at the
input of the gate. Any voltage above this level will not be treated as a logic
0 input by the logic circuit.
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 Digital IC Specification
 Voltage parameters:
• VIH(min): It is the maximum voltage level that can be treated as logic 0 at the output
of the gate. Any voltage above this level will not be treated as a logic 0 output.

 Current parameters:
• IIH: The current that flows into an input when a specified HIGH level voltage
is applied to that input.
• IIL: The current that flows into an input when a specified LOW level voltage
is applied to that input.
• I0H: The current that flows from an output in a logic 1 state under specified
load conditions.
• IoL: The current that flows from an output in a logic 0 state under specified
load conditions.

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 Digital IC Specification
 Noise Margin:
• When the digital circuits operate in noisy environment the gates may
malfunction if the noise is beyond certain limits.
• The noise immunity of a logic circuit refers to the circuit's ability to tolerate
noise voltages at its inputs.
• A quantitative measure of noise immunity is called noise margin.
 Operating Temperatures:
• The IC gates and other circuits are temperature sensitive being
semiconductor devices.
• However, they are designed to operate satisfactorily over a specified range
of temperature.
• The range specified for commercial applications is 0 to 70°C, for industrial it
is 0 to 85°C, and for military applications it is -55°C to 125°C.

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 Digital IC Specification
 Speed power products:
• A common means for measuring and comparing the overall performance of
an IC family is the speed power product, which is obtained by multiplying
the gate propagation delay by the gate power dissipation.
• A low value of speed power product is desirable. The smaller the product,
the better the overall performance.
• It is figure of merit of an IC family.

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 TTL v/s CMOS v/s ECL
Characteristic TTL CMOS ECL
Power Input Moderate Low Moderate-High
Frequency limit High Moderate Very high
Circuit density Moderate-high High-very high Moderate
Circuit types per family High High Moderate

Logic Propagation Power Noise Fan-in Fan-out Cost

Family delay time dissipation per Margin (V)
(ns) gate (mW)
TTL 9 10 0.4 8 10 Low
CMOS <50 0.01 5 10 50 Low
ECL 1 50 0.25 5 10 High

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 Transistor Transistor Logic (TTL)
 Dependence on transistors alone to perform basic logic
operations.
 Most popular logic family.
 Most widely useful bipolar digital IC family.
 The TTL uses transistors operating in saturated mode.
 It is the fastest of the saturated logic families.
 Good speed, low manufacturing cost, wide range of circuits, and
the availability in SSI and MSI are its merits.

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 Schottky TTL
 When a transistor is saturated, excess charge carries will be stored
in the base region and they must be removed before the transistor
can be turned off.
 So, owing to storage time delay, the speed is reduced.
 The Schottky TTL series reduces this storage time delay by not
allowing the transistor to go into full saturation.
 This is accomplished by using a Schottky barrier diode(SBD)
between the base and the collector of each transistor.
 More than three times the switching speed of standard TTL, at the
expense of approximately doubling the power consumption.

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 Tri-state TTL
 It utilizes the advantage of the high speed of operation of the
totem-pole configuration and wire ANDing of the open-collector
configuration.
 It is called the tri-state TTL, because it allows three possible
output states: HIGH, LOW, and HIGH Impedance (Hi-Z).
 In the Hi-Z state, both the transistors in the totem-pole
arrangement are turned off, so that the output terminal is a HIGH
impedance to ground or Vcc.
 In fact, the output is an open or floating terminal, that is, neither a
LOW nor a HIGH.

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125