Fault Modeling

 Why model faults?

 Some real defects in VLSI and PCB
 Common fault models
 Stuck-at faults
 Single stuck-at faults
 Fault equivalence
 Fault dominance and checkpoint theorem
 Classes of stuck-at faults and multiple faults
 Transistor faults
 Summary
 Review exercise
 2 Why Model Faults?

 I/O function tests inadequate for manufacturing (functionality

versus component and interconnect testing)
 Real defects (often mechanical) too numerous and often not
analyzable
 A fault model identifies targets for testing
 A fault model makes analysis possible
 Effectiveness measurable by experiments
 3
Defect, Fault, and Error
• Defect
• A defect is the unintended difference between the implemented hardware and
its intended design.
• Defects occur either during manufacture or during the use of devices.
• Fault
• A representation of a defect at the abstracted function level.
• Error
• A wrong output signal produced by a defective system.
• An error is caused by a Fault or a design error.
Some Real Defects in Chips
4
 Processing defects
 Missing contact windows
 Parasitic transistors
 Oxide breakdown
 ...
 Material defects
 Bulk defects (cracks, crystal imperfections)
 Surface impurities (ion migration)
 ...
 Time-dependent failures
 Dielectric breakdown
 Electromigration
 ...
 Packaging failures
 Contact degradation
 Seal leaks
 ...

Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -

Semiconductor Devices and Circuits, Wiley, 1981.
 5 Observed PCB Defects
Defect classes Occurrence frequency (%)

Shorts 51
Opens 1
Missing components 6
Wrong components 13
Reversed components 6
Bent leads 8
Analog specifications 5
Digital logic 5
Performance (timing) 5

Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

 6 Common Fault Models
 Single stuck-at faults
 Transistor open and short faults
 Memory faults
 PLA faults (stuck-at, cross-point, bridging)
 Functional faults (processors)
 Delay faults (transition, path)
 Analog faults
 For more details of fault models, see
M. L. Bushnell and V. D. Agrawal, Essentials of Electronic
Testing for Digital, Memory and Mixed-Signal VLSI Circuits,
Springer, 2000.
7 Objective

 Given a digital logic gate, what tests are to be performed to

assure an acceptable quality of product at reasonable price
 8 Single Stuck-at Fault
 Three properties define a single stuck-at fault
 Only one line is faulty
 The faulty line is permanently set to 0 or 1
 The fault can be at an input or output of a gate
 Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults

Faulty circuit value

Good circuit value
c j
0(1)
s-a-0
a d 1(0)
1 g h
z
0 1 i
b e 1
f k
Test vector for h s-a-0 fault
 9 Fault Equivalence
 Number of fault sites in a Boolean gate circuit is = #PI +
#gates + # (fanout branches)
 Fault equivalence: Two faults f1 and f2 are equivalent if all tests that
detect f1 also detect f2.
 If faults f1 and f2 are equivalent then the corresponding faulty functions
are identical.
 Fault collapsing: All single faults of a logic circuit can be divided into
disjoint equivalence subsets, where all faults in a subset are mutually
equivalent. A collapsed fault set contains one fault from each
equivalence subset.
 10 Equivalence Rules
sa0 sa0
sa1 sa1
sa0 sa1 sa0 sa1 WIRE
sa0 sa1 sa0 sa1
AND OR

sa0 sa1 sa0 sa1

sa0 sa1
NOT sa0
sa1

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1 sa0
NAND NOR
sa1
sa0 sa1 sa0
sa0 sa1
sa1
sa0
FANOUT sa1
 11 Equivalence Example
Faults in boldface
sa0 sa1 removed by
sa0 sa1 equivalence
sa0 sa1 collapsing
sa0 sa1 sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1
sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ── = 0.625
32
 12 Fault Dominance
 If all tests of some fault F1 detect another fault F2, then F2 is said to
dominate F1.
 Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed
from the fault list.
 When dominance fault collapsing is used, it is sufficient to consider only
the input faults of Boolean gates. See the next example.
 In a tree circuit (without fanouts) PI faults form a dominance collapsed
fault set.
 If two faults dominate each other then they are equivalent.
13 Dominance Example
All tests of F2
F1
s-a-1 001
F2
s-a-1 110 010
000
101 011
100

s-a-1 Only test of F1

s-a-1
s-a-1
s-a-0
A dominance collapsed fault set
 14 Dominance Example
sa0 sa1 Faults in red
sa0 sa1
removed by
sa0 sa1
equivalence
sa0 sa1 sa0 sa1 collapsing
sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1
sa0 sa1

sa0 sa1 sa0 sa1 Faults in yellow

sa0 sa1 removed by
sa0 sa1 dominance
sa0 sa1 collapsing
sa0 sa1
15
Collapse ratio = ── = 0.47
32
 15 Checkpoints
 Primary inputs and fanout branches of a
combinational circuit are called checkpoints.
 Checkpoint theorem: A test set that detects all
single (multiple) stuck-at faults on all checkpoints
of a combinational circuit, also detects all single
(multiple) stuck-at faults in that circuit.

Total fault sites = 16

Checkpoints ( ) = 10
Classes of Stuck-at Faults
16

 Following classes of single stuck-at faults are identified by fault

simulators:
 Potentially-detectable fault -- Test produces an unknown (X) state at primary output
(PO); detection is probabilistic, usually with 50% probability.
 Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected
as a potentially-detectable fault.
 Hyperactive fault -- Fault induces much internal signal activity without reaching PO.
 Redundant fault -- No test exists for the fault.
 Untestable fault -- Test generator is unable to find a test.
 17 Multiple Stuck-at Faults
 A multiple stuck-at fault means that any set of lines is stuck-at some
combination of (0,1) values.
 The total number of single and multiple stuck-at faults in a circuit
k
with k single fault sites is 3 -1.
 A single fault test can fail to detect the target fault if another fault is
also present, however, such masking of one fault by another is rare.
 Statistically, single fault tests cover a very large number of multiple
faults.
Transistor (Switch) Faults
18

 MOS transistor is considered an ideal switch and two types of faults

are modeled:
 Stuck-open -- a single transistor is permanently stuck in the open state.
 Stuck-short -- a single transistor is permanently shorted irrespective of its gate
voltage.
 Detection of a stuck-open fault requires two vectors.
 Detection of a stuck-short fault requires the measurement of
quiescent current (IDDQ).
Stuck-Open Example
19

Vector 1: test for A s-a-0

(Initialization vector)
Vector 2 (test for A s-a-1)
pMOS VDD Two-vector s-op test
FETs
can be constructed by
1 0
A ordering two s-at tests
Stuck-
open
0 0
B
C
0 1(Z)

Good circuit states

nMOS
FETs Faulty circuit states
Stuck-Short Example
20

Test vector for A s-a-0

pMOS VDD
FETs IDDQ path in
A faulty circuit
1 Stuck-
short

0
B Good circuit state
C
0 (X)

nMOS
FETs Faulty circuit state
 21 Summary
 Fault models are analyzable approximations of defects and are
essential for a test methodology.
 For digital logic single stuck-at fault model offers best advantage of
tools and experience.
 Many other faults (bridging, stuck-open and multiple stuck-at) are
largely covered by stuck-at fault tests.
 Stuck-short and delay faults and technology-dependent faults require
special tests.
 Memory and analog circuits need other specialized fault models and
tests.
 22 Review Exercise
 What are three most common types of blocks a modern SOC is likely to have?
Circle three: analog circuit,
digital logic, fluidics, memory, MEMS, optics, RF.
 The cost of a chip is US$1.00 when its yield is 50%. What will be its cost if you
increased the yield to 80%.
 What is the total number of single stuck-at faults, counting both stuck-at-0 and
stuck-at-1, in the following circuit?
 23 Answers
 What are three most common types of blocks a modern SOC is likely to have?
Circle three: analog circuit,
digital logic, fluidics, memory, MEMS, optics, RF.
 The cost of a chip is US$1.00 when its yield is 50%. What will be its cost if you
increased the yield to 80%.

Assume a wafer has n chips, then

wafer cost
Chip cost = ──────── = $1.00
0.5 × n

Wafer cost = 0.5n × $1.00 = 50n cents

For yield = 0.8, chip cost = wafer cost/(0.8n) = 50n/(0.8n) = 62.5 cents
 24 Answers Continued
 What is the total number of single stuck-at faults, counting both stuck-at-0 and
stuck-at-1, in the following circuit?

Counting two faults on each line,

Total number of faults = 2 × (#PI + #gates + #fanout branches)

= 2 × (2 + 2 + 2) = 12

s-a-0 s-a-1
s-a-0 s-a-1
s-a-0 s-a-1 s-a-0 s-a-1 s-a-0 s-a-1

s-a-0 s-a-1