ADC , Analog Comparator

& Input Capture

 ADC Interfacing
• Characteristics of ADC
– Resolution
– Conversion time
– Vref
– Digital Data Output
– Parallel Vs Serial ADC
– Analog Input Channels
– Start Conversion and End-of-Conversion

• Successive Approximation ADC

 ADC Programming in AVR
• Features
• 10-bit Resolution
• 8 Multiplexed Single Ended Input Channels
• 7 Differential Input Channels
• 2 Differential Input Channels with Optional Gain of 10x and
200x
• Optional Left adjustment for ADC Result Readout
• 0 - VCC ADC Input Voltage Range
• Selectable 2.56V ADC Reference Voltage
• Free Running or Single Conversion Mode
• ADC Start Conversion by Auto Triggering on Interrupt Sources
• Interrupt on ADC Conversion Complete
• Sample and Hold Circuit
ADC Multiplexer Selection Register – ADMUX

• Bit 7:6 – REFS1:0: Reference Selection Bits

– These bits select the voltage reference for the ADC.
– If these bits are changed during a conversion, the change will
not go in effect until this conversion is complete.
– The internal voltage reference options may not be used if an
external reference voltage is being applied to the AREF pin.
ADC Reference Source Selection
• Bit 5 – ADLAR: ADC Left Adjust Result
– The ADLAR bit affects the presentation of the ADC
conversion result in the ADC Data Register.
– Write one to ADLAR to left adjust the result.
Otherwise, the result is right adjusted.
• Bits 4:0 – MUX4:0: Analog Channel and Gain
Selection Bits
– The value of these bits selects which combination
of analog inputs are connected to the ADC.
– These bits also select the gain for the differential
channels.
ADC Input Channel Selection
 ADC Control and Status Register A – ADCSRA

• Bit 7 – ADEN: ADC Enable

– Writing this bit to one enables the ADC.
– By writing it to zero, the ADC is turned off.

• Bit 6 – ADSC: ADC Start Conversion

– To start conversion write this bit as 1.

• Bit 5 – ADATE: ADC Auto Trigger Enable

– When this bit is written to one, Auto Triggering of the ADC is enabled.
– The ADC will start a conversion on a positive edge of the selected
trigger signal.
• Bit 4 – ADIF: ADC Interrupt Flag
– This bit is set when an ADC conversion completes and the Data
Registers are updated.
– The ADC Conversion Complete Interrupt is executed if the ADIE bit
and the I-bit in SREG are set.
– Beware that if doing a Read-Modify- Write on ADCSRA, a pending
interrupt can be disabled.

• Bit 3 – ADIE: ADC Interrupt Enable

– When this bit is written to one and the I-bit in SREG is set, the ADC
Conversion Complete Interrupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

– These bits determine the division factor between the XTAL frequency
and the input clock to the ADC.
 Starting a Conversion
• Modes of Conversion :
– A single conversion
– Auto Triggering mode
• Free Running Mode

– A single conversion
• A single conversion is started by writing a logical one to the ADC Start
Conversion bit, ADSC.

• This bit stays high as long as the conversion is in progress and will be
cleared by hardware when the conversion is completed.

• If a different data channel is selected while a conversion is in progress,

the ADC will finish the current conversion before performing the
channel change.
– Auto Triggering
• Auto Triggering is enabled by setting the ADC Auto Trigger
Enable bit, ADATE in ADCSRA.

• The trigger source is selected by setting the ADC Trigger

Select bits, ADTS in SFIOR.

• When a positive edge occurs on the selected trigger

signal, the ADC prescaler is reset and a conversion is
started.

• This provides a method of starting conversions at fixed

intervals.
Auto Trigger Logic
 Special Function IO Register – SFIOR

• Bit 7:5 – ADTS2:0: ADC Auto Trigger Source

– If ADATE in ADCSRA is written to one, the value of these bits selects which
source will trigger an ADC conversion.

– If ADATE is cleared, the ADTS2:0 settings will have no effect.

– A conversion will be triggered by the rising edge of the selected Interrupt

Flag.
ADC Auto Trigger Source Selections
– Free Running mode
• Note that an Interrupt Flag will be set even if the specific interrupt is
disabled or the global interrupt enable bit in SREG is cleared.

• A conversion can thus be triggered without causing an interrupt.

• However, the Interrupt Flag must be cleared in order to trigger a new

conversion at the next interrupt event.

• Using the ADC Interrupt Flag as a trigger source makes the ADC start a
new conversion as soon as the ongoing conversion has finished.

• The ADC then operates in Free Running mode, constantly sampling and
updating the ADC Data Register.

• The first conversion must be started by writing a logical one to the ADSC
bit in ADCSRA.
Prescaling and Conversion Timing

ADC Prescaler
• The ADC module contains a prescaler, which generates an
acceptable ADC clock frequency from any CPU frequency above
100kHz.

• A normal conversion takes 13 ADC clock cycles.

• The first conversion after the ADC is switched on (ADEN in

ADCSRA is set) takes 25 ADC clock cycles in order to initialize the
analog circuitry.

• The actual sample-and-hold takes place 1.5 ADC clock cycles

after the start of a normal conversion and 13.5 ADC clock cycles
after the start of a first conversion.

• When a conversion is complete, the result is written to the ADC

Data Registers, and ADIF is set.
ADC Timing Diagram, First Conversion
ADC Timing Diagram, Single Conversion
ADC Timing Diagram, Auto Triggered Conversion
ADC Timing Diagram, Free Running Conversion
ADC Conversion Time
• WAP to get data from channel 0 and display
the result on PORT B and PORT D.

– ADMUX

– ADCSRA
 Analog Comparator

Analog Comparator Block Diagram

• SFIOR - Special Function IO Register

 Bit 3 – ACME: Analog Comparator Multiplexer

Enable
• When this bit is written logic one and the ADC is
switched off (ADEN in ADCSRA is zero), the ADC
multiplexer selects the negative input to the
Analog Comparator.

• When this bit is written logic zero, AIN1 is applied

to the negative input of the Analog Comparator.
• Analog Comparator Multiplexed Input
• ACSR - Analog Comparator Control and Status Register

– Bit 7 – ACD: Analog Comparator Disable

• When this bit is written logic one, the power to the
Analog Comparator is switched off.

– Bit 6 – ACBG: Analog Comparator Bandgap Select

• When this bit is set, a fixed bandgap reference voltage
replaces the positive input to the Analog Comparator.
• When this bit is cleared, AIN0 is applied to the
positive input of the Analog Comparator.
– Bit 5 – ACO: Analog Comparator Output
• The output of the Analog Comparator is synchronized
and then directly connected to ACO.

– Bit 4 – ACI: Analog Comparator Interrupt Flag

• This bit is set by hardware when a comparator output
event triggers the interrupt mode defined by ACIS1 and
ACIS0.

– Bit 3 – ACIE: Analog Comparator Interrupt Enable

• When the ACIE bit is written logic one and the I-bit in the
Status Register is set, the Analog Comparator Interrupt is
activated.
– Bit 2 – ACIC: Analog Comparator Input Capture Enable
• When written logic one, this bit enables the Input Capture
function in Timer/Counter1 to be triggered by the Analog
Comparator.
• To make the comparator trigger the Timer/Counter1 Input
Capture interrupt, the TICIE1 bit in the Timer Interrupt
Mask Register (TIMSK) must be set.

– Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt

Mode Select
 Input Capture Unit
• The Timer/Counter incorporates an Input Capture unit
that can capture external events and give them a time-
stamp indicating time of occurrence.

• The external signal indicating an event, or multiple events,

can be applied via the ICP1 pin or alternatively, via the
Analog Comparator unit.

• The time-stamps can then be used to calculate frequency,

duty-cycle, and other features of the signal applied.

• Alternatively the time-stamps can be used for creating a

log of the events.
Input Capture Unit Block Diagram
• Noise Canceler :
– The noise canceler improves noise immunity by using
a simple digital filtering scheme.

– The noise canceler input is monitored over four

samples, and all four must be equal for changing the
output that in turn is used by the edge detector.

– When enabled the noise canceler introduces

additional four system clock cycles of delay from a
change applied to the input, to the update of the ICR1
Register.

– The noise canceler uses the system clock and is

therefore not affected by the prescaler.
• TCCR1A - Timer/Counter1 Control Register A

• Bit 7:6 – COM1A1:0: Compare Output Mode for Compare unit A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Compare unit B
• Bit 3 – FOC1A: Force Output Compare for Compare unit A
• Bit 2 – FOC1B: Force Output Compare for Compare unit B
• Bit 1:0 – WGM11:0: Waveform Generation Mode
• TCCR1B - Timer/Counter1 Control Register B

• Bit 7 – ICNC1: Input Capture Noise Canceler

• Bit 6 – ICES1: Input Capture Edge Select
– When the ICES1 bit is written to zero, a falling (negative)
edge is used as trigger, and when the ICES1 bit is written
to one, a rising (positive) edge will trigger the capture.

– The event will also set the Input Capture Flag (ICF1), and
this can be used to cause an Input Capture Interrupt, if
this interrupt is enabled.
Waveform Generation Mode Bit Description