William Stallings

Computer Organization
and Architecture

Chapter 3
Top Level View of Computer
Function and Interconnection
 Top Level View of Computer Function and
Interconnection

3.1 Computer Components

3.2 Computer Function
Instruction Fetch and Execute
Interrupts
I/O Function
3.3 Interconnection Structures
3.4 Bus Interconnection
Bus Structure
Multiple-Bus Hierarchies
Elements of Bus Design
3.5 PCI
Bus Structure
PCI Commands
Data Transfers
Arbitration
Interrupt
 Virtually all computers provide a mechanism by which
other modules (I/O, memory) may interrupt the normal
processing of the CPU
 We need to introduce the concept to understand more
clearly the nature of the instruction cycle
 We focus on the communication between modules that
results from interrupts
 Interrupts are provided primarily as a way to improve
processing efficiency
Interrupt
 Most external devices are much slower than the processor
 Suppose that the processor is transferring data to a printer
 After each write operation, the processor must pause and
remain idle until the printer reads the data
 The length of this pause may be on the order of many
hundreds or even thousands of instruction cycles
 Clearly, this is a very wasteful use of the processor!
Interrupt
 If we make the processor execute instructions during the
pause period, this will be more efficient
 But how to notify the processor that the requested I/O
operation is completed ?
 I/O device send a signal to the processor indicating the
completion of I/O request
 This signal is called Interrupt signal
 It interrupts the normal execution, so processor can
finish the I/O operation correctly
Program example with I/O operations
I/O  The user program performs a series of Write calls
User Program
Program interleaved with processing
1  Code segments 1, 2, and 3 do not involve I/O.
4  The WRITE calls are to an I/O program that is a
Write
system utility and that will perform the actual I/O
operation
I/O
command With consists
 The I/O program interrupts, the
of three sections:
2
Done
processor
1. Segment 4 prepares can
for the be I/O operation
actual
5 engaged in executing
2. The actual I/O command
 other instructions
Once this command is issued, the program must wait
END
while
for the I/O antoI/O
device operation
perform the requested function
Write  is in
Wait can be done by progress
periodically poll the device
3. Segment 5 completes the operation
 This may include setting a flag indicating the success
3 or failure of the operation
 User program is stopped at the point of the Write
call for some considerable period of time
Write
Example Without Interrupts
Without
User Program I/O Interrupt 𝑻 (𝝁 𝒔)
Program
1 300
1 4 50
4 I/O operation
Write 400
CPU wait

5 50
I/O
command
Done
2 2 600

5 4 50
I/O operation
END 400
CPU wait

Write 5 50

3 600

3
Total=2500us

I/O wait 5 4 3 2 1 Code Segment

Write 400 50 50 600 600 300

Example With Interrupts
Without with
User Program
I/O Interrupt Interrupt 𝑻 (𝝁 𝒔)
Program

1 1 300
1 4 4 50
4 I/O operation concurrent
Write
I/O operation
CPU wait 2a 400
with processor execution
5 5 50
I/O
command 2b 200
2a Done 4 50
2 I/O operation concurrent
END
3a 400
with processor execution
X 4
5 50
2b Interrupt I/O operation
CPU wait
3b 200
Handler Total=1700us
5
Write
5
3a 3
END
X Total=2500us
3b I/O wait 5 4 3 2 1 Code Segment

Write 400 50 50 600 600 300

Example With Interrupts (long I/O)
Without With long
User Program
I/O Interrupt I/O 𝑻 (𝝁 𝒔)
Program

1 1 300
1 4 4 50
4
Write

I/O wait
2 600 I/O operation concurrent
with processor execution
I/O Then processor waits
command
Done 200
I/O wait
5
5 50
2 END 4 50

2
Interrupt
3 600
I/O operation concurrent
with processor execution
Handler 4 Then processor waits

Write I/O wait 200

I/O wait
5 5 50
Total=2100us

END
3 Total=3300us

I/O wait 5 4 3 2 1 Code Segment

Write 50 50 600 600 300 800

Interrupt mechanism
 With interrupts, the processor can be engaged in executing
other instructions while an I/O operation is in progress
 The I/O program that is invoked in this case consists only
of the preparation code and the actual I/O command
 This I/O operation is conducted concurrently with the
execution of instructions in the user program
 When the external device becomes ready to be serviced, the
I/O module for that external device sends an interrupt
request signal to the processor
 The processor responds by suspending operation of the
current program, branching off to a program to service that
particular I/O device, known as an interrupt handler
 Processor resumes execution after the device is serviced
Interrupt
 From the point of view of the user program, an interrupt is
just that:
 An interruption of the normal sequence of execution.
 When the interrupt processing is completed, execution resumes
 Thus, the user program does not have to contain any special
code to accommodate interrupts;
 Processor and the operating system are responsible for
suspending user program then resuming it at the same point
User Program
Interrupt handler
Instruction 1
Instruction 1
Instruction 2
Instruction 2

Interrupt Instruction i Instruction n

occurs here
Instruction i+1

Instruction m
Instruction Cycle
 To accommodate interrupts, an interrupt cycle is added to the
instruction cycle

Interrupts
disabled
Fetch Next Execute Check for interrupt;
Start Instruction Instruction Interrupts process interrupt
enabled

Halt

Fetch cycle Execute cycle Interrupt cycle

Interrupt Cycle
 Processor checks to see if any interrupts have occurred,
indicated by the presence of an interrupt signal
 If no interrupts are pending, the processor proceeds to the
fetch cycle and fetches the next instruction of current program
 If an interrupt is pending, the processor does the following:
 Suspends execution of the current program and saves its context
 It sets the PC to the starting address of an interrupt handler routine
 The processor now proceeds to the fetch cycle and fetches the
first instruction in the interrupt handler program

Save its context

 Saving the address of the next instruction
to be executed (PC) and
 Any other data relevant to the processor’s
current activity
Interrupt Handler
 It is also called Interrupt Service Routine (ISR)
 Typically, this program determines the nature of the interrupt
and performs whatever actions are needed.
 In our example, the handler determines which I/O module
generated the interrupt and may branch to a program that will
write more data out to that I/O module.
 When interrupt handler routine is completed, the processor
resumes execution of user program at the point of interruption
 It is clear that there is some overhead involved in this process.
 Extra instructions must be executed (in the interrupt handler)

 Nevertheless, because of the relatively large amount of time

wasted on an I/O operation, the processor can be employed
much more efficiently with the use of interrupts.
Instruction cycle state diagram with interrupt
Interrupt Sources
Multiple Interrupts
 For example, a program may be receiving data from a
communications line and printing results.
 The printer will generate an interrupt every time it completes a
print operation.
 The communication line controller will generate an interrupt
every time a unit of data arrives.
 The unit could either be a single character or a block,
depending on the nature of the communications discipline.
 In any case, it is possible for a communications interrupt to
occur while a printer interrupt is being processed
 This situation is called multiple interrupts
 How to process multiple interrupts?
 Two approaches can be taken to dealing with multiple
interrupts
Multiple Interrupts
 The first is to disable interrupts while an interrupt is being
processed
 Thus, when a user program is executing and an interrupt occurs,
interrupts are disabled immediately.
 After the interrupt handler routine completes, interrupts are enabled
before resuming the user program, and the processor checks to see if
additional interrupts have occurred
Interrupt are handled in strict
 This approach is nice and simple, as interrupts
Handler X
sequential order
User Program Disable interrupts

Interrupt Y
occurs here
Interrupt X
Enable interrupts Interrupt
occurs here
Handler Y
Disable interrupts

Enable interrupts
Multiple Interrupts
 The drawback to the preceding approach is that it does not take into
account relative priority or time-critical needs
 when input arrives from the communications line, it may need to be
absorbed rapidly to make room for more input.
 If the first batch of input has not been processed before the second
batch arrives, data may be lost
 A second approach is to define priorities for interrupts and to allow
an interrupt of higher priority to interrupt a lower-priority interrupt
Interrupt
Handler X
Higher
User Program Priority
Interrupt Y
occurs here Interrupt
Handler Y
Interrupt X
occurs here
Multiple Interrupts
 Consider a system with three I/O devices: a printer, a disk, and a
communications line, with priorities of 2, 4, and 5, respectively
disk Comm printer user
4 5 2 0 Priority
User Program 20 15 10 0 Time
10 10 10 50 duration

Printer ISR Comm ISR

Disk
printer
𝒕 =𝟏𝟎 Comm
𝒕 =𝟏𝟓 𝒕 =𝟐𝟎
𝒕 =𝟐𝟓
Disk ISR
𝒕=𝟒𝟎

𝒕 =𝟑𝟓
I/O Function and DMA
 The role of I/O is discussed in detail in Chapter 7
 I/O instructions similar to memory reference instruction is
used to exchange data with I/O device
 In some cases, it is desirable to allow I/O exchanges to occur
directly with memory.
 In such a case, the processor grants to an I/O module the
authority to read from or write to memory
 During such a transfer, the I/O module issues read or write
commands to memory directly.
 This operation is known as direct memory access (DMA)
 It is a very useful technique for massive data transfer