Lecture

Lecture 3
3
Combinational
Combinational Automatic
Automatic
Test-Pattern
Test-Pattern Generation
Generation
(ATPG)
(ATPG)
 ATPG System
 Representations
 Completeness
 Algebras
 Types of Algorithms

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 1

 ATPG
ATPG Problem
Problem
 ATPG: Automatic test pattern generation
Given
 A circuit (usually at gate-level)
 A fault model (usually stuck-at type)
Find
 A set of input vectors to detect all modeled faults.
 Core problem: Find a test vector for a given fault.
 Combine the “core solution” with a fault
simulator into an ATPG system.

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 2

 What
What is
is Test?
Test?
Fault activation
Fault effect
X Combinational circuit
1
0
0 1/0 1/0
Primary inputs Primary outputs
1
(PI) (PO)
0
1
X
X

Path sensitization
Stuck-at-0 fault

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 3

 ATPG
ATPG is
is a
a Search
Search Problem
Problem
 Search the input vector space for a test:
 Initialize all signals to unknown (X) state – complete
vector space is the playing field
 Activate the given fault and sensitize a path to a PO –
narrow down to one or more tests

Vector Vector
Space Circuit Space Circuit

X X
X 0
sa1 sa1 0/1
X 1

001 101

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 4

 Need
Need to
to Deal
Deal With
With Two
Two
Copies
Copies of
of the
the Circuit
Circuit
Good circuit
X X
Alternatively, use a multi-valued
0
algebra of signal values for both
0

Different outputs
good and faulty circuits.
1
Same input

Circuit
Faulty circuit
X X
X X
0
0 0/1
sa1
sa1 1 1
1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 5

 Circuit
Circuit and
and Binary
Binary
Decision
Decision Tree
Tree

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 6

 Binary
Binary Decision
Decision Diagram
Diagram
 BDD – Follow path from source to sink node –
product of literals along path gives Boolean
value at sink
 Rightmost path: A B C = 1
 Problem: Size varies greatly
with variable order

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 7

 Algorithm
Algorithm Completeness
Completeness
 Definition: Algorithm is complete if it
ultimately can search entire binary
decision tree, as needed, to generate a
test
 Untestable fault – no test for it even after
entire tree searched
 Combinational circuits only – untestable
faults are redundant, showing the
presence of unnecessary hardware

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 8

 Algebras:
Algebras: Roth’s
Roth’s 5-Valued
5-Valued
and
and Muth’s
Muth’s 9-Valued
9-Valued
Symbol Alternative Fault-free Faulty
Representation circuit Circuit
D 1/0 1 0
D
0/1 0 1
0 Roth’s
1
0/0 0 0
Algebra
X 1/1 1 1
G0 X/X X X
G1 0/X 0 X
Muth’s
F0 1/X 1 X
Additions
F1 X/0 X 0
X/1 X 1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 9

 Roth’s
Roth’s and
and Muth’s
Muth’s
Higher-Order
Higher-Order Algebras
Algebras
 Represent two machines, which are simulated
simultaneously by a computer program:
 Good circuit machine (1st value)
 Bad circuit machine (2nd value)
 Better to represent both in the algebra:
 Need only 1 pass of ATPG to solve both
 Good machine values that preclude bad machine
values become obvious sooner & vice versa
 Needed for complete ATPG:
 Combinational: Multi-path sensitization, Roth Algebra
 Sequential: Muth Algebra -- good and bad machines
may have different initial values due to fault

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 10

 Function
Function of
of NAND
NAND Gate
Gate
Input a
c
0 1 X D D
D
1/0 0 1 1 1 1 1
a
1
c
0/1
b 1 1 0 X D D
D Input b
X 1 X X X X

D 1 D X D 1

D 1 D X 1 D

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 11

 Exhaustive
Exhaustive Algorithm
Algorithm


For n-input circuit, generate all 2n input
patterns
 Infeasible, unless circuit is partitioned into
cones of logic, with  15 inputs
 Perform exhaustive ATPG for each cone
 Misses faults that require specific
activation patterns for multiple cones to
be tested

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 12

Random-Pattern
Random-Pattern Generation
Generation
 Flow chart for
method
 Use to get
tests for 60-
80% of faults,
then switch
to D-algorithm
or other ATPG
for rest

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 13

Boolean
Boolean Difference
Difference Symbolic
Symbolic
Method (Sellers et
Method (Sellers et al
al.)
.)

g = G (X1, X2, …, Xn) for the fault site

fj = Fj (g, X1, X2, …, Xn)
1  j  m
Xi = 0 or 1 for 1 i n

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 14
 Boolean
Boolean Difference
Difference
(Sellers,
(Sellers, Hsiao,
Hsiao, Bearnson)
Bearnson)
 Shannon’s Expansion Theorem:
F (X1, X2, …, Xn) = X2 F (X1, 1, …, Xn) + X2 F (X1, 0, …, Xn)
 
 Boolean Difference (partial derivative):

 Fj = F (1, X , X , …, X ) F (0, X , …, X )
j 1 2 n  j 1 n
 g
 Fault Detection Requirements:
G (X1, X2, …, Xn) = 1
 F = F (1, X , X , …, X ) F (0, X , …, X ) = 1
j j 1 2 n  j 1 n
g
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 15
Path
Path Sensitization
Sensitization Method
Method
Circuit
Circuit Example
Example
1 Fault Sensitization
2 Fault Propagation
3 Line Justification

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 16

Path
Path Sensitization
Sensitization Method
Method
Circuit
Circuit Example
Example
 Try path f – h – k – L blocked at j, since
there is no way to justify the 1 on i

1 D

D D
1 D
D 1 0

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 17

Path
Path Sensitization
Sensitization Method
Method
Circuit
Circuit Example
Example
 Try simultaneous paths f – h – k – L and
g – i – j – k – L blocked at k because
D-frontier (chain of D or D) disappears
1 D
D
1 1
D D D
1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 18

Path
Path Sensitization
Sensitization Method
Method
Circuit
Circuit Example
Example
 Final try: path g – i – j – k – L – test found!

0
0 D
1 D
D D D
1
1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 19

 Forward
Forward Implication
Implication
 Results in logic gate inputs
that are significantly
labeled so that output is
uniquely determined
 AND gate forward
implication table:

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 20

 Backward
Backward Implication
Implication
 Unique determination of all gate inputs when
the gate output and some of the inputs are given

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 21

 Implication
Implication Stack
Stack
 Push-down stack. Records:
 Each signal set in circuit by ATPG
 Whether alternate signal value already tried
 Portion of binary search tree already searched

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 22

 Implication
Implication Stack
Stack after
after
Backtrack
Backtrack

Unexplored
Present Assignment 0 E 1
Searched and Infeasible
B B
0 1 0 1

F F F
0 1 0 1 0 1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 23

Objectives
Objectives and
and Backtracing
Backtracing
of
of ATPG
ATPG Algorithm
Algorithm
 Objective – desired signal value goal for ATPG
 Guides it away from infeasible/hard solutions
 Backtrace – Determines which primary input and
value to set to achieve objective
 Use testability measures

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 24

 Branch-and-Bound
Branch-and-Bound Search
Search
 Efficiently searches binary search tree
 Branching – At each tree level, selects
which input variable to set to what value
 Bounding – Avoids exploring large tree
portions by artificially restricting search
decision choices
 Complete exploration is impractical
 Uses heuristics

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 3 25