AVR

Interrupts and Timer/Counter

AVR ATmega
INTERRUPTS
Interrupts
Definition of ‘Interrupt’

Event that disrupts the normal execution of a program

and causes the execution of special instructions

3
Interrupts

Program

time t

4
Interrupts

Interrupt

Program

time t

5
Interrupts

Interrupt

Program Program

Interrupt Service Routine

time t

6
Interrupts in the ATmega
 Many possible interrupt sources
 One interrupt vector for each source
 Interrupt vector table shown in datasheet

Vector # Address Source Defnition

10 $0012 PCINT0 Pin change interrupt
25 $0030 SPI, STC SPI serial transfer complete
30 $003A ADC ADC conversion complete

 Source+”_vect” is the interrupt name recognized by your

compiler
 Check notes on this (avr-libc manual)
Interrupt Vectors
Interrupt handling with the AVR-Libc API

Interrupt and Signal definitions: <avr/interrupt.h>

● remember: vector table points to interrupt routines

● by using the appropriate name, your routine will be

installed in the table and called when the interrupt occurs

● a set of default interrupt routines is provided

● Macro for registering interrupt routines: ISR

(<signalname>)

● Saving and restoring registers is handled

Interrupt handling with the AVR-Libc API

Example interrupt handler for the ADC:

#include <avr/interrupt.h>

ISR(ADC_vect)
{
// user code here
}

● The interrupt source, here the ADC, has to be configured

and enabled using SFRs

● Global interrupt instructions: sei () … set interupt enable

(I – bit in SREG) cli () … clear interrupt enable

● AVR hardware clears the global interrupt flag before entering an

interrupt vector -> use sei() to enable nested interrupts
Enabling/Disabling Interrupts
 ATmega contains a status register called SREG
 Bit 7 of SREG , the I bit, is the Global Interrupt Enable
 Clearing I bit disables interrupts, setting I bit enables
them
 I bit is automatically cleared when an interrupt starts, set
when interrupt is done
• Interrupts are not interrupted
 Use the SEI() and CLI() macros to set and clear in C
Defining Interrupts in C
ISR(vector_name)
- Defines an ISR for vector_name. Updates interrupt vector table
automatically.
Ex. ISR(ADC_vect) {
printf(“Hello, world.”);
}

EMPTY_INTERRUPT(vector_name)
- Defines an interrupt which does nothing.
 Internal Interrupts
• ATmega328p has 20 internal interrupts.
• These internal interrupts are generated by the
internalperipherals of Microcontroller like Timer,
ADC, serial, eeprom etc.
• The internal interrupts are used for efficient
operation of the internal peripherals.
• They can be enabled through the registers of these
peripherals
 External Interrupts
• Triggered by the INT pins or any of the PCINT pins. The
PinChange Interrupt Request 2 (PCI2) will trigger if any enabled
PCINT[23:16] pin toggles.
• The Pin Change Interrupt Request 1 (PCI1) will trigger if any
enabled PCINT[14:8] pin toggles.
• The Pin Change Interrupt Request 0 (PCI0) will trigger if any
enabled PCINT[7:0] pin toggles.The PCMSK2, PCMSK1 and
PCMSK0 Registers control which pins contribute to the
pinchange interrupts. Pin change interrupts on PCINT are
detected asynchronously.
• The External Interrupts can be triggered by a falling or rising
edge or a low level. This is set upas indicated in the
specification for the External Interrupt Control Register A
(EICRA
 How to use interrupts
• Configure and enable the global interrupts. SREG I Bit
• Write functions called Interrupt Service Routine (ISR) to
handle interrupts. (defined outside the main function)
• Enable external interrupts locally in External Interrupt
Mask Register (EIMSK).
• Configure the interrupts for falling edge, rising edge, low
level or any logical change by using EICRA register.
• Enable the internal interrupts locally by writing 1 to
interrupt enable bit in the registersof the peripheral under
use. For example, ADC system consists of ADIE bit
inADCSRA register. ADIE bit is enabled to use ADC
interrupts
External Interrupts – eg. On INT0
 Registers for External interrupt
• EICRA: External Interrupt Control Register A
• EIMSK: External Interrupt Mask Register
Timer/Counter
• Timer/Counter 0
• 8 bit
• Timer/Counter 1
• 16 bit
• Timer/Counter 2
• 8 bit
8-bit Timer/Counter0 with PWM
• Features
• Single Compare Unit Counter
• Clear Timer on Compare Match (Auto Reload)
• Phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• External Event Counter
• 10-bit Clock Prescaler (1, 8, 64, 256, 1024)
• Overflow and Compare Match Interrupt Sources (TOV0
and OCF0)
Setting Prescalar
How much prescalar is needed?
- Can the counter count for 1000ms?
- 16 bits, 65,536 is max value
- System clock period is 1/50kHz = 20 microseconds
- 65,536 * 20 microseconds = 1.31 seconds
- 1.31 sec > 1000ms, so no prescalar is needed
 Setting Prescalar
How much prescalar is needed?
- Can the counter count for 1000ms?
- 16 bits, 65,536 is max value
- System clock period is 1/50kHz = 20 microseconds
- 65,536 * 20 microseconds = 1.31 seconds
- 1.31 sec > 1000ms, so no prescalar is needed
Timer0
 Timer Registers
• The Timer/Counter (TCNT0) and Output Compare
Register (OCR0) are 8-bit registers.
• Interrupt request signals are all visible in the Timer
Interrupt Flag Register (TIFR).
• All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSK).
• TIFR and TIMSK are not shown in the figure since
these registers are shared by other timer units.
Registers
• The Timer/Counter can be clocked internally, via the
prescaler, or by an external clock source on the T0 pin.
• The Clock Select logic block controls which clock
source and edge the Timer/Counter uses to increment
(or decrement) its value.
• The Timer/Counter is inactive when no clock source is
selected.
• The output from the Clock Select logic is referred to as
the timer clock (clkT0)
Registers
• The double buffered Output Compare Register (OCR0)
is compared with the Timer/Counter value at all times
• The result of the compare can be used by the
waveform generator to generate a PWM or variable
frequency output on the Output Compare Pin (OC0)
• The compare match event will also set the Compare
Flag (OCF0) which can be used to generate an output
compare interrupt request
Registers used in
timers/counters
• TCCR0 – Timer/Counter Control Register
• TCNT0 – Timer/Counter Register
• OCR0 – Output Compare Register
• TIMSK – Timer/Counter Interrupt Mask Register
• TIFR – Timer/Counter Interrupt Flag Register
Mode Timer/Counter 0
• Normal
• CTC (Clear Timer on Compare Match)
• Fast PWM (Single Slope PWM)
• Phase Correct PWM (Double Slope PWM)
TCCR0 – Timer/Counter Control
Register
 Bit 7 – FOC0: Force Output Compare
• The FOC0 bit is only active when the WGM00 bit specifies a
non-PWM mode
• However, for ensuring compatibility with future devices, this bit must
be set to zero when TCCR0 is written when operating in PWM mode.
• When writing a logical one to the FOC0 bit, an immediate
compare match is forced on the Waveform Generation unit.
• The OC0 output is changed according to its COM01:0 bits
setting. Note that the FOC0 bit is implemented as a strobe.
• Therefore it is the value present in the COM01:0 bits that determines
the effect of the forced compare.
• A FOC0 strobe will not generate any interrupt, nor will it clear
the timer in CTC mode using OCR0 as TOP
Bit 3, 6 – WGM0[1:0]: Waveform
Generation Mode
Bit 5:4 – COM01:0: Compare Match
Output Mode
• Pin OC0 , mode Fast PWM
• Pin OC0 , mode Phase Correct PWM
 Bit 2:0 – CS02:0: Clock Select
• TimerClock = {Off, fc, fc/8, fc/64, fc/256, fc/1024}
TIMSK – Timer/Counter Interrupt
Mask Register
TIFR – Timer/Counter Interrupt Flag
Register
 Normal Mode
• The simplest mode of operation is the normal mode
(WGM01:0 = 0).
• In this mode the counting direction is always up
(incrementing), and no counter clear is performed.
• The counter simply overruns when it passes its
maximum 8-bit value (TOP = 0xFF) and then restarts
from the bottom (0x00).
Normal Mode
• In normal operation the Timer/Counter Overflow
Flag (TOV0) will be set in the same timer clock cycle
as the TCNT0 becomes zero.
• The TOV0 Flag in this case behaves like a ninth bit,
except that it is only set, not cleared.
 Clear Timer on Compare Match
(CTC) Mode
• In Clear Timer on Compare or CTC mode (WGM01:0
= 2), the OCR0 Register is used to manipulate the
counter resolution.
• In CTC mode the counter is cleared to zero when the
counter value (TCNT0) matches the OCR0
CTC Mode
• The OCR0 defines the top value for the counter,
hence also its resolution.
• This mode allows greater control of the compare
match output frequency
CTC Mode
• The timing diagram for the CTC mode is shown
below
• The counter value (TCNT0) increases until a
compare match occurs between TCNT0 and OCR0,
and then counter (TCNT0) is cleared
// in order to function as a time delay at the beginning of the main loop
// NOTE: 1ms = 0xF9 but we are going 0xFF, so we are actually creating a
// 1.024ms timer.
#include <avr/io.h>
int main(void)
{
while (1)
{
// start the timer

TCCR0 |= (1 << CS01) | (1 << CS00);

// set prescaler to 64 and start the timer

while ( (TIFR & (1 << TOV0) ) > 0) // wait for the overflow event
{
}

TIFR &= ~(1 << TOV0);

// reset the overflow flag
}
}
// this code sets up a timer0 for 4ms @ 16Mhz clock cycle
// an interrupt is triggered each time the interval occurs.
#include <avr/io.h>
#include <avr/interrupt.h>
int main(void)
{
TIMSK |= (1 << TOIE0);

sei(); //enable interrupts

TCCR0 |= (1 << CS02);

// set prescaler to 256 and start the timer
while (1)
{
//main loop }
}
ISR (TIMER0_OVF_vect) // timer0 overflow interrupt
{
// event to be executed every 4ms here
}
 16-bit Timer/Counter1
• Features
• True 16-bit Design (i.e., Allows 16-bit PWM)
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B,
and ICF1)
Diagram Timer/Counter 16 bit
 TCNT1 – 16 Bit
• The TCNT1H Register can only be indirectly accessed
by the CPU.
• When the CPU does an access to the TCNT1H I/O
location, the CPU accesses the High byte temporary
register (TEMP).
• The temporary register is updated with the TCNT1H
value when the TCNT1L is read, and TCNT1H is
updated with the temporary register value when
TCNT1L is written.
TCNT1 – 16 Bit
• This allows the CPU to read or write the entire 16-
bit counter value within one clock cycle via the 8-
bit data bus.
• It is important to notice that there are special cases
of writing to the TCNT1 Register when the counter
is counting that will give unpredictable results.
• The special cases are described in the sections
where they are of importance.
Input Capture Unit
• The Timer/Counter incorporates an Input Capture
unit that can capture external events and give them
a time-stamp indicating time of occurrence.
• The external signal indicating an event, or multiple
events, can be applied via the ICP1 pin or
alternatively, via the Analog Comparator unit.
Input Capture Unit
• The time-stamps can then be used to calculate
frequency, duty-cycle, and other features of the
signal applied.
• Alternatively the time-stamps can be used for
creating a log of the events.
Output Compare Units
• The OCR1x Register is double buffered when using
any of the twelve Pulse Width Modulation (PWM)
modes.
• For the normal and Clear Timer on Compare (CTC)
modes of operation, the double buffering is
disabled.
• The double buffering synchronizes the update of
the OCR1x Compare Register to either TOP or
BOTTOM of the counting sequence.
• The synchronization prevents the occurrence of
odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
Double Buffered OCRnx
 OCR
• The OCR1x Register access may seem complex, but
this is not case.
• When the double buffering is enabled, the CPU has
access to the OCR1x Buffer Register, and if double
buffering is disabled the CPU will access the OCR1x
directly.
• The content of the OCR1x (Buffer or Compare)
Register is only changed by a write operation (the
Timer/Counter does not update this register
automatically as the TCNT1 and ICR1 Register).
OCR
• Therefore OCR1x is not read via the High byte
temporary register (TEMP).
• However, it is a good practice to read the Low byte first
as when accessing other 16-bit registers.
• Writing the OCR1x Registers must be done via the
TEMP Register since the compare of all 16 bits is
done continuously.
OCR
• The High byte (OCR1xH) has to be written first.
When the High byte I/O location is written by the
CPU, the TEMP Register will be updated by the
value written.
• Then when the Low byte (OCR1xL) is written to the
lower eight bits, the High byte will be copied into
the upper 8-bits of either the OCR1x buffer or
OCR1x Compare Register in the same system clock
cycle.
Accessing 16-bit Registers
• The TCNT1, OCR1A/B, and ICR1 are 16-bit registers
that can be accessed by the AVR CPU via the 8-bit
data bus.
• The 16-bit register must be byte accessed using
two read or write operations.
• Each 16-bit timer has a single 8-bit register for
temporary storing of the High byte of the 16-bit
access.
• The same temporary register is shared between all
16-bit registers within each 16-bit timer.
Accessing 16-bit Registers
• Accessing the Low byte triggers the 16-bit read or
write operation.
• When the Low byte of a 16-bit register is written by the
CPU, the High byte stored in the temporary register, and
the Low byte written are both copied into the 16-bit
register in the same clock cycle.
• When the Low byte of a 16-bit register is read by the
CPU, the High byte of the 16-bit register is copied into
the temporary register in the same clock cycle as the
Low byte is read.
Accessing 16-bit Registers
• Not all 16-bit accesses uses the temporary register
for the High byte.
• Reading the OCR1A/B 16-bit registers does not involve
using the temporary register.
• To do a 16-bit write, the High byte must be written
before the Low byte.
• For a 16-bit read, the Low byte must be read before
the High byte.
Accessing 16-bit Registers
• The following code examples show how to access
the 16-bit Timer Registers assuming that no
interrupts updates the temporary register.
• The same principle can be used directly for
accessing the OCR1A/B and ICR1 Registers.
• Note that when using “C”, the compiler handles the
16-bit access.
Registers
• TCCR1A – Timer/Counter1 Control Register A
• TCCR1B – Timer/Counter1 Control Register B
• TCNT1H and TCNT1L –Timer/Counter1 High and
Low Register
• OCR1AH and OCR1AL – Output Compare Register 1
A
• OCR1BH and OCR1BL – Output Compare Register 1
B
• ICR1H and ICR1L – Input Capture Register 1
• TIMSK – Timer/Counter Interrupt Mask Register
• TIFR – Timer/Counter Interrupt Flag Register
 Mode Timer/Counter 1
• Normal, TOP FFFFH
• CTC
• TOP: ICR1, OCR1A
• Fast PWM
• TOP: ICR1, OCR1A, 8-bit, 9-bit, 10-bit
• Phase Correct PWM
• TOP: ICR1, OCR1A, 8-bit, 9-bit, 10-bit
• Phase and Frequency Correct
• TOP: ICR1, OCR1A
 TCCR1A – Timer/Counter1 Control
Register A

• Bit 7:6 – COM1A1:0: Compare Output Mode for

Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for
Channel B
• Bit 3 – FOC1A: Force Output Compare for Channel
A
• Bit 2 – FOC1B: Force Output Compare for Channel B
• Bit 1:0 – WGM11:0: Waveform Generation Mode
 TCCR1B – Timer/Counter1 Control
Register B

• Bit 7 – ICNC1: Input Capture Noise Canceler

• Bit 6 – ICES1: Input Capture Edge Select
• Bit 5 – Reserved Bit
• Bit 4:3 – WGM13:2: Waveform Generation Mode
• Bit 2:0 – CS12:0: Clock Select
 TCNT1H and TCNT1L –Timer/Counter1
High and Low Register
• The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined
TCNT1) give direct access, both for read and for write operations, to the
Timer/Counter unit 16-bit counter.
• To ensure that both the high and Low bytes are read and written
simultaneously when the CPU accesses these registers, the access is
performed using an 8-bit temporary High Byte Register (TEMP).
• This temporary register is shared by all the other 16-bit registers.
• Modifying the counter (TCNT1) while the counter is running introduces a
risk of missing a compare match between TCNT1 and one of the OCR1x
Registers.
• Writing to the TCNT1 Register blocks (removes) the compare match on the
following timer clock for all compare units.
OCR1AH and OCR1AL – Output Compare
Register 1 A
OCR1BH and OCR1BL – Output Compare
Register 1 B
• The Output Compare Registers contain a 16-bit value
that is continuously compared with the counter value
(TCNT1).
• A match can be used to generate an output compare
interrupt, or to generate a waveform output on the
OC1x pin.
ICR1H and ICR1L – Input Capture
Register 1
• The Input Capture is updated with the counter
(TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the analog comparator
output for Timer/Counter1).
• The Input Capture can be used for defining the
counter TOP value.
 TIMSK – Timer/Counter Interrupt
Mask Register

• Bit 5 – TICIE1: Timer/Counter1, Input Capture

Interrupt Enable
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A
Match Interrupt Enable
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B
Match Interrupt Enable
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt
Enable
 TIFR – Timer/Counter Interrupt Flag
Register

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

• Bit 4 – OCF1A: Timer/Counter1, Output Compare A
Match Flag
• Bit 3 – OCF1B: Timer/Counter1, Output Compare B
Match Flag
• Bit 2 – TOV1: Timer/Counter1, Overflow Flag
Timing
• Normal
• CTC
• Fast PWM
Registers
• TCCR2 – Timer/Counter Control Register
• TCNT2 – Timer/Counter Register
• OCR2 – Output Compare Register
• ASSR – Asynchronous Status Register
• TIMSK – Timer/Counter Interrupt Mask Register
• TIFR – Timer/Counter Interrupt Flag Register
• SFIOR – Special Function IO Register
 TCCR2 – Timer/Counter Control
Register

• Bit 7 – FOC2: Force Output Compare

• Bit 3, 6 – WGM2[1:0]: Waveform Generation Mode
• Bit 5:4 – COM21:0: Compare Match Output Mode
• Bit 2:0 – CS22:0: Clock Select
 ASSR – Asynchronous Status
Register

• Bit 3 – AS2: Asynchronous Timer/Counter2

• Bit 2 – TCN2UB: Timer/Counter2 Update Busy
• Bit 1 – OCR2UB: Output Compare Register2 Update
Busy
• Bit 0 – TCR2UB: Timer/Counter Control Register2
Update Busy
Bit 3 – AS2: Asynchronous
Timer/Counter2
• When AS2 is written to zero, Timer/Counter 2 is
clocked from the I/O clock, clkI/O.
• When AS2 is written to one, Timer/Counter2 is
clocked from a Crystal Oscillator connected to the
Timer Oscillator 1 (TOSC1) pin.
• When the value of AS2 is changed, the contents of
TCNT2, OCR2, and TCCR2 might be corrupted.
• Bit 2 – TCN2UB: Timer/Counter2
Update Busy
• When Timer/Counter2 operates asynchronously
and TCNT2 is written, this bit becomes set.
• When TCNT2 has been updated from the
temporary storage register, this bit is cleared by
hardware.
• A logical zero in this bit indicates that TCNT2 is
ready to be updated with a new value.
• Bit 1 – OCR2UB: Output Compare
Register2 Update Busy
• When Timer/Counter2 operates asynchronously
and OCR2 is written, this bit becomes set.
• When OCR2 has been updated from the temporary
storage register, this bit is cleared by hardware.
• A logical zero in this bit indicates that OCR2 is ready
to be updated with a new value.
• Bit 0 – TCR2UB: Timer/Counter
Control Register2 Update Busy
• When Timer/Counter2 operates asynchronously and TCCR2 is written,
this bit becomes set.
• When TCCR2 has been updated from the temporary storage register,
this bit is cleared by hardware.
• A logical zero in this bit indicates that TCCR2 is ready to be updated
with a new value.
• If a write is performed to any of the three Timer/Counter2 Registers
while its update busy flag is set, the updated value might get corrupted
and cause an unintentional interrupt to occur.
• The mechanisms for reading TCNT2, OCR2, and TCCR2 are different.
• When reading TCNT2, the actual timer value is read. When reading
OCR2 or TCCR2, the value in the temporary storage register is read.
 TIMSK – Timer/Counter Interrupt
Mask Register

• Bit 7 – OCIE2: Timer/Counter2 Output Compare

Match Interrupt Enable
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt
Enable
 TIFR – Timer/Counter Interrupt Flag
Register

• Bit 7 – OCF2: Output Compare Flag 2

• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
Bit 7 – OCF2: Output Compare Flag
2
• The OCF2 bit is set (one) when a compare match
occurs between the Timer/Counter2 and the data
in OCR2 – Output Compare Register2. OCF2 is
cleared by hardware when executing the
corresponding interrupt handling vector.
• Alternatively, OCF2 is cleared by writing a logic one
to the flag.
• When the I-bit in SREG, OCIE2 (Timer/Counter2
Compare match Interrupt Enable), and OCF2 are
set (one), the Timer/Counter2 Compare match
Interrupt is executed
Bit 6 – TOV2: Timer/Counter2
Overflow Flag
• The TOV2 bit is set (one) when an overflow occurs in
Timer/Counter2. TOV2 is cleared by hardware when
executing the corresponding interrupt handling vector.
• Alternatively, TOV2 is cleared by writing a logic one to the
flag.
• When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow
Interrupt Enable), and TOV2 are set (one), the
Timer/Counter2 Overflow interrupt is executed.
• In PWM mode, this bit is set when Timer/Counter2 changes
counting direction at $00.
 SFIOR – Special Function IO
Register

• Bit 1 – PSR2: Prescaler Reset Timer/Counter2

• When this bit is written to one, the Timer/Counter2
prescaler will be reset.
• The bit will be cleared by hardware after the operation is
performed.
• Writing a zero to this bit will have no effect.
• This bit will always be read as zero if Timer/Counter2 is
clocked by the internal CPU clock.
• If this bit is written when Timer/Counter2 is operating in
asynchronous mode, the bit will remain one until the
prescaler has been reset.
Timer 1 Initialization
void InitTimer0( void )
{
TCCR0A = 0b00000000;
// No compare output, no waveform gen
TCCR0B = 0b00000001;
// No forcing, No prescalar
OCR0A = TIMER0_CNT;
// Load Compare value for timer 0
TIMSK0 = _BV(OCIE0A);
// enable compare-match interrupt
// _BV(n) == (1 << n)
TCNT0 = 0;
// Initialize timer to 0
}