Input / Output

Mahadik R.V.
 I/O Hardware
• Human readable
– used to communicate with the user
– video display terminals
– keyboard, mouse
– printer
• Machine readable
– used to communicate with electronic equipment
– disk drives, tape drives, modems
– serial, parallel, network ports
– controllers
2
 Differences Among I/O Devices
• Data Transfer Rate
• Application
– disk used to store files / disk used to store
virtual memory pages
• Complexity of control
• Unit of transfer
• Data representation (encoding schemes)
• Error conditions (devices respond to errors
differently)
cs431-cotter 3
 I/O Devices

Figure 5-1. Some

typical device,
network, and bus
data rates.

4
 I/O Hardware Concepts
• Bus (shared direct access or daisy chain)

CPU
monitor cache
graphics bridge scsi
memory controller
controller controller

IDE disk PCI Bus keyboard

expansion
controller
bus serial port
cs431-cotter 5
 I/O Hardware Concepts
• Bus (shared direct access or daisy chain)
• Port

CPU
monitor cache
graphics bridge scsi
memory controller
controller controller

IDE disk PCI Bus keyboard

expansion
controller
bus serial port
cs431-cotter 6
 I/O Hardware Concepts
• Bus (shared direct access or daisy chain)
• Port
• Controller
CPU
monitor cache
graphics bridge scsi
memory controller
controller controller

IDE disk PCI Bus keyboard

expansion
controller
bus serial port
cs431-cotter 7
 Application I/O Interface
• Objective of the I/O system is to encapsulate
individual device behaviors in generic classes.
• The device driver layer hides the differences
among I/O controllers from the kernel
• Devices vary in many dimensions
– Character-stream vs Block devices
– Sequential vs Random-access location
– Synchronous vs Asynchronous data transfer
– Sharable vs Dedicated I/O device
– Read, Write, or Read/Write
cs431-cotter 8
 Kernel I/O Structure
Device Drivers
kernel

Kernel I/O Subsystem

SCSI keyboard mouse PCI bus floppy ATAPI
device device device ... device device device
driver driver driver driver driver driver

SCSI keyboard mouse PCI bus floppy ATAPI

device device device ... device device device
contrlr contrlr contrlr contrlr contrlr contrlr

SCSI
keyboard mouse floppy ATAPI
device ... PCI bus
drive devices

cs431-cotter 9
 Software I/O Techniques
• Polling (programmed I/O)
– send command and wait
• Interrupt Driven I/O
– send command and continue
• Direct Memory Access (DMA)
– Use separate processor to manage I/O

cs431-cotter 10
 Polling
• CPU determines state of I/O device
– Status register
• To send data to I/O device:
– Host reads busy bit until clear.
– Host sets write bit and sends data to data-out
register
– Host sets command-ready bit
– Controller sets busy bit
– Controller reads command register and sees write
command
– Controller reads data in data-out register and clears
command-ready, error, and busy when complete
cs431-cotter 11
 Programmed I/O (1)

Figure 5-7. Steps in printing a string.

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 Programmed I/O (2)

Figure 5-8. Writing a string to the printer using programmed I/O.

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 Interrupt Driven I/O
• Interrupts are handled through an interrupt
controller
• Types of interrupts
– nonmaskable - invalid address, divide by zero, etc
– maskable - device controllers
• Identification of interrupts
– Interrupt vector: Addresses of each interrupt
handling routine.
– Interrupt priority implicit in vector

cs431-cotter 14
 Interrupt Driven I/O

device driver
initiates I/O
initiates I/O

Receives Int., when complete,

transfers to Int generates int.
handler

Int. handler
processes data

resume processing
of interrupted task
I/O Controller
cs431-cotter CPU 15
 Interrupt Driven I/O

device driver
initiates I/O
initiates I/O

Receives Int., when complete,

transfers to Int generates int.
handler

Int. handler
processes data

resume processing
of interrupted task
I/O Controller
cs431-cotter CPU 16
 Interrupt Driven I/O

device driver
initiates I/O
initiates I/O

Receives Int., when complete,

transfers to Int generates int.
handler

Int. handler
processes data

resume processing
of interrupted task
I/O Controller
cs431-cotter CPU 17
 Interrupt Driven I/O

device driver
initiates I/O
initiates I/O

Receives Int., when complete,

transfers to Int generates int.
handler

Int. handler
processes data

resume processing
of interrupted task
I/O Controller
cs431-cotter CPU 18
 Interrupt Driven I/O

device driver
initiates I/O
initiates I/O

Receives Int., when complete,

transfers to Int generates int.
handler

Int. handler
processes data

resume processing
of interrupted task
I/O Controller
cs431-cotter CPU 19
 Interrupt Driven I/O

device driver
initiates I/O
initiates I/O

Receives Int., when complete,

transfers to Int generates int.
handler

Int. handler
processes data

resume processing
of interrupted task
I/O Controller
cs431-cotter CPU 20
 Interrupt Handlers (1)
1. Save registers not already been saved by
interrupt hardware.
2. Set up a context for the interrupt service
procedure.
3. Set up a stack for the interrupt service procedure.
4. Acknowledge the interrupt controller. If there is
no centralized interrupt controller, reenable
interrupts.
5. Copy the registers from where they were saved to
the process table.

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 Interrupt Handlers (2)
6. Run the interrupt service procedure.
7. Choose which process to run next.
8. Set up the MMU context for the process to
run next.
9. Load the new process’ registers, including its
PSW.
10. Start running the new process.

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 Direct Memory Access
• Takes control of the system from the CPU to
transfer data to and from memory over the
system bus
• Cycle stealing is used to transfer data on the
system bus
• The instruction cycle is suspended so data can
be transferred
• The CPU pauses one bus cycle
• No interrupts occur
– No need to save context
cs431-cotter 23
 DMA Transfer Process
Device driver gets command to transfer data (C bytes)
from disk to memory buffer (address X)

processor
monitor

graphics scsi
DMA memory
controller controller

PCI Bus
IDE disk keyboard
expansion
controller
bus serial port
disk disk
cs431-cotter 24
 DMA System Architecture
Device driver instructs disk controller to
transfer data from disk to buffer in memory

processor
monitor

graphics scsi
DMA memory
controller controller

PCI Bus
IDE disk keyboard
expansion
controller
bus serial port
disk disk
cs431-cotter 25
 DMA System Architecture
Disk controller initiates DMA transfer

processor
monitor

graphics scsi
DMA memory
controller controller

PCI Bus
IDE disk keyboard
expansion
controller
bus serial port
disk disk
cs431-cotter 26
 DMA System Architecture
Disk controller sends each byte to DMA controller

processor
monitor

graphics scsi
DMA memory
controller controller

PCI Bus
IDE disk keyboard
expansion
controller
bus serial port
disk disk
cs431-cotter 27
 DMA System Architecture
DMA controller transfers data to memory,
adjusting addresses and sizes accordingly

processor
monitor

graphics scsi
DMA memory
controller controller

PCI Bus
IDE disk keyboard
expansion
controller
bus serial port
disk disk
cs431-cotter 28
 DMA System Architecture
When C = 0, DMA interrupts to signal
completion of DMA transfer

processor
monitor

graphics scsi
DMA memory
controller controller

PCI Bus
IDE disk keyboard
expansion
controller
bus serial port
disk disk
cs431-cotter 29
 Typical DMA Block Diagram
The processor identifies whether a read or write is requested,
and loads starting memory address, byte count, I/O address

Data
Count

Data Lines Data

Register

Address
Address Lines Register

DMA Request

DMA Acknowledge

Interrupt Control
Logic
Read

Write

cs431-cotter 30
 Typical DMA Block Diagram
I/O device initiates DMA Request. DMA controller seizes
memory bus, returns ACK. I/O sends data thru DMA

Data
Count

Data
Data
Register
Lines

Address
Address Lines Register

DMA Request

DMA Acknowledge

Interrupt Control
Logic
Read

Write

cs431-cotter 31
 Typical DMA Block Diagram
When data transfer is complete, DMA signals with interrupt

Data
Count

Data Lines Data

Register

Address
Address Lines Register

DMA Request

DMA Acknowledge

Interrupt Control
Logic
Read

Write

cs431-cotter 32
 DMA Transfer Process
• Device driver gets command to transfer data (C bytes)
from disk to memory buffer (address X)
• Device driver instructs disk controller to transfer data from
disk to buffer in memory
• Disk controller initiates DMA transfer
• Disk controller sends each byte to DMA controller
• DMA controller transfers data to memory, adjusting
addresses and sizes accordingly
• When C = 0, DMA interrupts to signal completion of DMA
transfer

cs431-cotter 33
 DMA / Interrupt Breakpoints

Time

Instruction Cycle

Processor Processor Processor Processor Processor Processor

Cycle Cycle Cycle Cycle Cycle Cycle

Fetch Decode Fetch Execute Store Process

Instruction Instruction Operand Instruction Result Interrupt

DMA Interrupt
Breakpoints Breakpoint

cs431-cotter 34
 DMA / Interrupt Breakpoints

Time

Instruction Cycle

Processor Processor Processor Processor Processor Processor

Cycle Cycle Cycle Cycle Cycle Cycle

Fetch Decode Fetch Execute Store Process

Instruction Instruction Operand Instruction Result Interrupt

DMA Interrupt
Breakpoints Breakpoint

cs431-cotter 35
Precise and Imprecise Interrupts
Properties of a precise interrupt

1. PC (Program Counter) is saved in a known

place.
2. All instructions before the one pointed to
by the PC have fully executed.
3. No instruction beyond the one pointed to
by the PC has been executed.
4. Execution state of the instruction pointed
cs431-cotter
to by the PC is known. 36
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 Factors affecting Interrupt state

• Pipeline CPU architecture

• Superscalar CPU architecture

• May leave some instructions partially executed

• Does not guarantee “first-come first-served”

• May require extensive state capture

• May require complex logic to capture precise state
cs431-cotter 37
Precise and Imprecise Interrupts (2)

Figure 5-6. (a) A precise interrupt. (b) An imprecise interrupt.

cs431-cotter 38
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 I/O Efficiency Improvement
• Reduce # of context switches
• Reduce # of data copies in memory as data
passes from device to application
• Reduce # of interrupts
– larger data transfers
– smart controllers
– polling (?)
• Use DMA (increase processing concurrency)
• Balance performance of CPU, memory, bus, I/O
cs431-cotter 39
 User-Space I/O Software

Figure 5-17. Layers of the I/O system and the

main functions of each layer.
cs431-cotter 40
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 Secondary Storage
• Basic structure
• SSDs
• Scheduling Algorithms
• Reliability

cs431-cotter 41
 Disk Structure
• Addressed as a large, 1 dimensional array of
logical blocks (clusters).
• Blocks are mapped onto disk sectors
– Mapping starts with track 0, head 0, sector 0.
– Continues through sectors on the same track
and head
– Moves to all heads on the same cylinder
– Moves to all cylinders in the drive

cs431-cotter 42
 Disk Mechanism

cs431-cotter 43
 Magnetic Disks (1)

Figure 5-18. Disk parameters for the original IBM PC 360-KB floppy disk
and a Western Digital WD 18300 hard disk.
cs431-cotter 44
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 Magnetic Disks (2)

Figure 5-19. (a) Physical geometry of a disk with two zones.

(b) A possible virtual geometry for this disk.
cs431-cotter 45
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CD-ROMs

Figure 5-21.
Recording
structure of a
compact disc
or CD-ROM.

cs431-cotter 46
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 CD-ROMs (2)

Figure 5-22. Logical data layout on a CD-ROM.

cs431-cotter 47
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 CD-Recordables

Figure 5-23. Cross section of a CD-R disk and laser. A silver

CD-ROM has similar structure, except without dye layer and with pitted aluminum layer instead
of gold layer.

cs431-cotter 48
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 DVD (1)

DVD Improvements on CDs

1. Smaller pits
(0.4 microns versus 0.8 microns for CDs).
2. A tighter spiral
(0.74 microns between tracks versus 1.6 microns
for CDs).
3. A red laser
(at 0.65 microns versus 0.78 microns for CDs).
cs431-cotter 49
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 DVD (2)

DVD Formats

1. Single-sided, single-layer (4.7 GB).

2. Single-sided, dual-layer (8.5 GB).
3. Double-sided, single-layer (9.4 GB).
4. Double-sided, dual-layer (17 GB).

cs431-cotter 50
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 DVD (3)

Figure 5-24. A double-sided, dual-layer DVD disk.

cs431-cotter 51
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 Solid State Devices
History
• ROM – Read Only Memory - ?
• PROM – Programmable Read Only Memory -
1956
• EPROM – Eraseable Programmable ROM - 1972
• EEPROM – Electrically Eraseable PROM – 1978

cs431-cotter 52
 Early SSD Issues
• Relatively Low Capacity
• Very Slow ”Erase” times
• High cost per bit.

cs431-cotter 53
 Flash Memory
• Developed ~1980
• Memory cells organized into Blocks
– Erase at block level
• Based on Floating-gate Transistors
– Stores a charge between insulating layers
– Can retain a charge “for many years”

cs431-cotter 54
 Floating-Gate Transistor

cs431-cotter 55
 Floating-Gate Transistor
• Multiple voltages needed to read / write /
erase
– Typically generated with circuitry on device
– Device typically requires standard PC voltages.
• Two types available
– Single Level Cell (SLC) only detects presence or
absence of current
– Multi-level Cell (MLC) detects current level,
allowing storage of multiple bits per cell
cs431-cotter 56
 SSD Organization

• Objective is to provide a structure that will

improve performance (write / erase)
• Stored in pages / blocks / planes
– Typical page sizes: 512 / 2048 / 4096 bytes
– Typical block sizes: 32 / 64 / 128 pages
– Typical plane sizes: 1024 / 2048 / ???
– 4096 * 128 * 2048 = 1 GB
• Memory chips may have multiple dies.
• Devices may have multiple chips.
cs431-cotter 57
 SSD Performance
Speed
SLC MLC

Read 25 μs 50 μs

Erase 2 ms per block 2 ms per block

Write 250 μs 900 μs

cs431-cotter 58
 SSD Performance
Endurance
• Bit level reliability
– SLC - ~100,000 program / erase cycles
– MLC - ~5,000 to 10,000 program / erase cycles
• Robust ECC
– Correct single bit errors
• Over-provision
– Mark bad memory and move data to good blocks
• Wear leveling
– Write data evenly across storage space
cs431-cotter 59
 SSD Products
• Current –
– OCZ Technology
• PCIe – Z-drives 256GB ($1300), 512 GB, 1TB
• 2.5” / 3.5” SATA – 250GB, 500GB, 1TB ($3900)
– Western Digital
• 2.5” SATA – 256GB ($800)
– Corsair , Kingston, Patriot, etc.
• Future
–?

cs431-cotter 60
 Hard Disk Formatting (1)

Figure 5-25. A disk sector.

cs431-cotter 61
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Disk Format

Figure 5-26. An
illustration of
cylinder
skew.

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 Disk Formatting (3)

Figure 5-27. (a) No interleaving. (b) Single interleaving.

(c) Double interleaving.

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 Disk Scheduling
• To read or write, the disk head must be
positioned at the desired track and at the
beginning of the desired sector

cs431-cotter 64
 Disk Scheduling
• To read or write, the disk head must be
positioned at the desired track and at the
beginning of the desired sector
• Seek time
– time it takes to position the head at the desired
track
• Rotational delay or rotational latency
– time its takes until desired sector is rotated to line
up with the head

cs431-cotter 65
 Disk Scheduling
• Access time
– sum of seek time and rotational delay
– the time it takes to get in position to read or write
• Data transfer occurs as the sector moves
under the head
• Data transfer for an entire file is faster when
the file is stored in the same cylinder and in
adjacent sectors

cs431-cotter 66
 Disk Scheduling
• Seek time is a reason for differences in
performance (try to minimize)
• For a single disk there will be a number of
I/O requests
• If requests are selected randomly, we will
get the worst possible performance

cs431-cotter 67
 Disk Scheduling - Objective
• Objective is to maximize disk bandwidth
– minimize “wasted” time
– seek time dominates

cs431-cotter 68
 Disk Scheduling - Objective
• Objective is to maximize disk bandwidth
– minimize “wasted” time
– seek time dominates
• Common example:
– disk head starts on track 53 (range 0 - 199)
– list of pending requests
98, 183, 37, 122, 14, 124, 65, 67

cs431-cotter 69
 Disk Scheduling - FCFS
• First-come, first-served (FCFS)
– Process request sequentially
– Fair to all processes
– Approaches random scheduling in performance if
there are many processes
– Avoids starvation
• Example head movement: 640 cylinders
track 53 - 98 - 183 - 37 - 122 - 14 - 124 - 65 - 67
 45 + 85 + 146 + 85 + 108 + 110 + 59 + 2 = 640

cs431-cotter 70
 Disk Scheduling - SSTF
• Shortest Service Time First
– select the disk I/O request that requires the
least movement of the disk arm from its
current position
– always choose the minimum Seek time
• Example head movement: 236 cylinders
– 53 - 65 - 67 - 37 - 14 - 98 - 122 - 124 - 183

cs431-cotter 71
Disk Arm Scheduling Algorithms (2)

Figure 5-28. Shortest Seek First (SSF) disk scheduling algorithm.

cs431-cotter 72
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 Disk Scheduling - SCAN
• SCAN
– arm moves in one direction only, satisfying all
outstanding requests until it reaches the last
track in that direction
– direction is reversed
– (also known as elevator algorithm)
• Example head movement: 236 cylinders
– 53 - 37 - 14 - 0 - 65 - 67 - 98 - 122 - 124 - 183

cs431-cotter 73
Disk Arm Scheduling Algorithms (3)

Figure 5-29. The elevator algorithm for scheduling disk requests.

cs431-cotter 74
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 Disk Scheduling - C-SCAN
• C-SCAN
– Provides a more uniform wait time than SCAN
– Restricts scanning to one direction only
– When the last track has been visited in one direction,
the arm is returned to the opposite end of the disk
and the scan begins again
– Treats the cylinders as a circular list that wraps
around from the last cylinder to the first one.
• Example head movement: 383 cylinders
53 - 65 - 67 - 98 - 122 - 124 - 183 - 199 - 0 - 14 - 37
cs431-cotter 75
 Disk Scheduling - C-LOOK
• C-LOOK
– version of C-SCAN
– Difference is that head arm only goes as far as the
last request in each direction. It doesn’t go to the
beginning or end of the disk automatically.
• Example head movement: 322 cylinders
53 - 65 - 67 - 98 - 122 - 124 - 183 - 14 - 37

cs431-cotter 76