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8086 Microprocessor 01

This document discusses memory interfacing with the 8086 microprocessor. It describes how the 8086 can access 1MB of memory using two 512KB memory chips. The lower 512KB bank is selected using the A0 address line, while the upper bank is selected using the /BHE (Bank High Enable) signal. It also explains that the 8086 has a 20-bit address bus, allowing it to access 2^20 = 1MB of address space using address lines A1 to A19 to drive the memory chips. The document provides examples of how to implement separate decoders and write strobes to interface with the lower and upper memory banks.

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12 views

8086 Microprocessor 01

This document discusses memory interfacing with the 8086 microprocessor. It describes how the 8086 can access 1MB of memory using two 512KB memory chips. The lower 512KB bank is selected using the A0 address line, while the upper bank is selected using the /BHE (Bank High Enable) signal. It also explains that the 8086 has a 20-bit address bus, allowing it to access 2^20 = 1MB of address space using address lines A1 to A19 to drive the memory chips. The document provides examples of how to implement separate decoders and write strobes to interface with the lower and upper memory banks.

Uploaded by

fa20-bce-047
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Microprocessor Systems and

Interfacing
CPE/EEE 342
Microprocessor 8086

 Outline
 Memory Interfacing with 8086 microprocessor

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8088 and 8086 Microprocessors

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Memory organization
1M bytes memory using 2 512K byte chips

Odd boundary
Address requires
2 cycles

BHE – bank high enable


Hardware organization
 In hardware, the 1M bytes memory is implemented
as two independent 512K-byte banks
 Low (even) bank, and the high (odd) bank
 Data from low bank use data bus 0-7
 Data from high bank use data bus 8-15
 Signal A0 enables the low bank
 Signal /BHE enables the high bank
 /BHE is active low
 How many address lines are required in order to
access 512K locations?
 (Ans. 19)
Memory organization
Only A1 to A19 are used to drive the memory !!!

High bank Low bank


Memory Interfacing with 8086 CPU

 BHE (Byte High Enable or Bank High Enable)

 Odd and Even bytes


 Role of A0
 16-bit data bus
 20-bit address bus

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Memory Interfacing

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Separate Bank Selection (Example)

 Separate decoders are required for each bank


 Example describes 1MB SRAM interfacing
with 8086 CPU
 Memory map for total memory will be
00000H to FFFFFH

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Memory Interfacing

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Separate Write Strobe Approach

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Memory Interfacing

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