EEL580 - Arquitetura de Computadores: Instructions -

Language of the Computer (1/2)

Docente: Diego L. C. Dutra

Sumário

● Instruction Set
● RISC-V Arithmetic Operations and Operands
● Representing Instructions in the Computer
● Logical Operations
● Instructions for Making Decisions
● Supporting Procedures in Computer Hardware
● RISC-V Instruction Encoding Summary
Instruction Set

● The repertoire of instructions of a ● The RISC-V Instruction Set

computer ○ Used as the example throughout the book
● Different computers have different ○ Developed at UC Berkeley as open ISA
instruction sets ○ Now managed by the RISC-V Foundation (
○ But with many aspects in common [Link])
● Early computers had very simple ○ Typical of many modern ISAs
instruction sets ○ See RISC-V Reference Data tear-out card
○ Simplified implementation ○ Similar ISAs have a large share of embedded
● Many modern computers also have core market
simple instruction sets ○ Applications in consumer electronics,
network/storage equipment, cameras,
printers, …
RISC-V Arithmetic Operations

● Add and subtract, three operands ● Arithmetic Example

○ Two sources and one destination ○ C code:
add a, b, c // a gets b + c f = (g + h) - (i + j);
● All arithmetic operations have this ○ Compiled RISC-V code:
form
● Design Principle 1: Simplicity favors add t0, g, h // temp t0 = g + h
regularity add t1, i, j // temp t1 = i + j
○ Regularity makes implementation
simpler sub f, t0, t1 // f = t0 - t1
○ Simplicity enables higher performance at
lower cost
RISC-V Register Operands

● Arithmetic instructions use register

operands
● RISC-V has a 32 × 64-bit register file
○ Use for frequently accessed data
○ 64-bit data is called a “doubleword”
■ 32 x 64-bit general purpose
registers x0 to x31
○ 32-bit data is called a “word”
● Design Principle 2: Smaller is
faster
○ c.f. main memory: millions of locations
RISC-V Register Operands Example

● Arithmetic Example w/o Registers ● Arithmetic Example w/ Registers

○ C code: ○ C code:

f = (g + h) - (i + j); f = (g + h) - (i + j);
○ Compiled RISC-V code: ■ f, …, j in x19, x20, …, x23
○ Compiled RISC-V code:
add t0, g, h // temp t0 = g + h
add x5, x20, x11
add t1, i, j // temp t1 = i + j
add x6, x22, x23
sub f, t0, t1 // f = t0 - t1
sub x19, x5, x6
Memory Operands

● Main memory used for composite data ● Memory Operand Example

○ Arrays, structures, dynamic data ○ C code:
● To apply arithmetic operations
○ Load values from memory into registers A[12] = h + A[8];
○ Store result from register to memory
■ h in x21, base address of A in x22
● Memory is byte addressed ○ Compiled RISC-V code:
○ Each address identifies an 8-bit byte ■ Index 8 requires offset of 64
● RISC-V is Little Endian ■ 8 bytes per doubleword
○ Least-significant byte at least address of a
word ld x9,
○ c.f. Big Endian: most-significant byte at least 64(x22)
address
● RISC-V does not require words to be add x9, x21, x9
aligned in memory
○ Unlike some other ISAs sd x9, 96(x22)
Registers vs. Memory

● Registers are faster to access than ● Immediate Operands

memory ○ Constant data specified in an
● Operating on memory data instruction
requires loads and stores
○
addi x22, x22, 4
More instructions to be executed
● Compiler must use registers for ○ Make the common case fast
variables as much as possible ■ Small constants are common
○ Only spill to memory for less ■ Immediate operand avoids
frequently used variables
○ Register optimization is important!
a load instruction
RISC-V: Encoding Schemes

● Integers
○ Unsigned Binary Integers: 0 to +2 n – 1
○ 2s-Complement Signed Integers: –2 n - 1 to +2n - 1 – 1
■ Sign Extension on load
● lb: sign-extend loaded byte
● lbu: zero-extend loaded byte
● Float Point: IEEE 754
○ Floating point (32-bit)
○ Floating point Double (64-bit)
○ Floating point Quad (128-bit)
● Instructions
○ ????
RISC-V R-format Instructions

● Instruction fields
○ opcode: operation code
○ rd: destination register number
○ funct3: 3-bit function code (additional opcode)
○ rs1: the first source register number
○ rs2: the second source register number
○ funct7: 7-bit function code (additional opcode)
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
● R-format Example
add x9,x20,x21

0000 0001 0101 1010 0000 0100 1011 00112 = 015A04B316

RISC-V I-format Instructions

● Immediate arithmetic and load instructions

○ rs1: source or base address register number
○ immediate: constant operand, or offset added to base address
■ 2s-complement, sign extended
● Design Principle 3: Good design demands good compromises
○ Different formats complicate decoding, but allow 32-bit instructions uniformly
○ Keep formats as similar as possible

immediate rs1 funct3 rd opcode

12 bits 5 bits 3 bits 5 bits 7 bits
addi x9, x9, 1

lw x9, 120(x10)
RISC-V S-format Instructions

● Different immediate format for store instructions

○ rs1: base address register number
○ rs2: source operand register number
○ immediate: offset added to base address
■ Split so that rs1 and rs2 fields always in the same place
imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

sw x9, 120(x10)
Stored Program Computers

The BIG ● Instructions represented in binary,

Picture just like data
● Instructions and data stored in
memory
● Programs can operate on
programs
○ e.g., compilers, linkers, …
● Binary compatibility allows
compiled programs to work on
different computers
○ Standardized ISAs
RISC-V Logical Operations

● Instructions for bitwise manipulation

I-format

R-format

○ Logical operators in common programming languages and their corresponding RISC-V instructions. One
way to implement NOT is to use XOR with one operand being all ones (FFFF FFFF FFFF FFFF 16).
● Useful for extracting and inserting groups of bits in a word
RISC-V Shift Operations

● immed: how many positions to shift

● Shift left logical
○ Shift left and fill with 0 bits
○ slli by i bits multiplies by 2i
● Shift right logical
○ Shift right and fill with 0 bits
○ srli by i bits divides by 2i (unsigned only)
● Modified I-Format

funct6 immed rs1 funct3 rd opcode

6 bits 6 bits 5 bits 3 bits 5 bits 7 bits
slli x11, x19, 4
Instructions for Making Decisions

● Branch to a labeled instruction if a ● Compiling If Statements

condition is true ○ C code:
○ Otherwise, continue sequentially if (i==j) f = g+h;
● beq rs1, rs2, L1 else f = g-h;
○ if (rs1 == rs2) branch to instruction labeled
L1 ■ f, g, … in x19, x20, …
● bne rs1, rs2, L1 ○ Compiled RISC-V code:
○ if (rs1 != rs2) branch to instruction labeled L1 bne x22, x23, Else
add x19, x20, x21
beq x0,x0,Exit
Else: sub x19, x20, x21
Exit: …
Assembler calculates addresses
Instructions for Making Decisions: Basic Blocks

● A basic block is a sequence of instructions with

○ No embedded branches (except at end)
○ No branch targets (except at beginning)
■ Microarchitectural attacks may violate this

● A compiler identifies basic blocks for

optimization
● An advanced processor can accelerate
execution of basic blocks
Instructions for Making Decisions: More Conditional Operations

● blt rs1, rs2, L1

○ if (rs1 < rs2) branch to instruction labeled L1
● bge rs1, rs2, L1
○ if (rs1 >= rs2) branch to instruction labeled L1
● Signed vs. Unsigned
○ Signed comparison: blt, bge
○ Unsigned comparison: bltu, bgeu
○ Example:
■ x22 = 1111 1111 1111 1111 1111 1111 1111 1111 ● Branch instructions specify
■ x23 = 0000 0000 0000 0000 0000 0000 0000 0001 ○ Opcode, two registers, target
■ x22 < x23 // signed address
■ –1 < +1 ○ Most branch targets are near branch
■ x22 > x23 // unsigned ○ Forward or backward
■ +4,294,967,295 > +1 ○ PC-relative addressing
■ Target address = PC +
immediate × 2

SB format:
Supporting Procedures in Computer Hardware: RISC-V Procedure Calling

● Steps required x5 – x7, x28 – x31: temporary registers

Not preserved by the callee
a. Place parameters in registers x10 to x17
b. Transfer control to procedure
c. Acquire storage for procedure
x8 – x9, x18 – x27: saved registers
d. Perform procedure’s operations If used, the callee saves and restores
e. Place result in register for caller them
f. Return to place of call (address in x1)

● Procedure call: jump and link jal x1, ProcedureLabel

○ Address of following instruction put in x1
○ Jumps to target address
● Procedure return: jump and link register jalr x0, 0(x1)
○ Like jal, but jumps to 0 + address in x1
○ Use x0 as rd (x0 cannot be changed)
○ Can also be used for computed jumps:
■ e.g., for case/switch statements
Supporting Procedures in Computer Hardware: RISC-V Procedure Calling - Example

● Leaf Procedure Example C code: ● Leaf Procedure Example RISC-V code:

int leaf_example( leaf_example:
addi sp,sp,-12 // adjust stack
int g, int h, int i, int j) {
sw x5,8(sp) // save register
int f; sw x6,4(sp) // save register
f = (g + h) - (i + j); sw x20,0(sp) // save register
return f; add x5,x10,x11
} add x6,x12,x1
sub x20,x5,x6
○ Arguments g, …, j in x10, …, x13 addi x10,x20,0
○ f in x20 lw x20,0(sp) // restore register
○ temporaries x5, x6 lw x6,4(sp) // restore register
○ Need to save x5, x6, x20 on stack lw x5,8(sp) // restore register
addi sp,sp,12 // adjust stack
jalr x0,0(x1) // return to calling
Supporting Procedures in Computer Hardware: RISC-V Procedure Calling - Local Data on the Stack

● Register Usage
○ x5 – x7, x28 – x31: temporary registers
■ Not preserved by the callee
○ x8 – x9, x18 – x27: saved registers
■ If used, the callee saves and restores them

● Stack grows down

○ addi sp, sp,-X
Supporting Procedures in Computer Hardware: RISC-V Procedure Calling - Non-Leaf Procedures

● Procedures that call other procedures

● For nested call, caller needs to save on the stack:
○ Its return address
○ Any arguments and temporaries needed after the call
● Restore from the stack after the call
Supporting Procedures in Computer Hardware: RISC-V Procedure Calling - Non-Leaf Procedures

● Example RISC-V code:

● Example C code: fact:
addi sp,sp,-8
int fact (int n){ sw x1,4(sp)
if (n < 1) return f; sw x10,0(sp)
else return n * fact(n - 1); addi x5,x10,-1
bge x5,x0,L1
} addi x10,x0,1
○ Argument n in x10 addi sp,sp,8
jalr x0,0(x1)
○ Result in x10 L1: addi x10,x10,-1
jal x1,fact
addi x6,x10,0
lw x10,0(sp)
lw x1,4(sp)
addi sp,sp,8
mul x10,x10,x6
jalr x0,0(x1)
Supporting Procedures in Computer Hardware: RISC-V Procedure Calling - Jump Addressing

● Jump and link (jal) target uses 20-bit immediate for larger range
○ U and UJ format:

● For long jumps, eg, to 32-bit absolute address

○ lui: load address[31:12] to temp register
○ jalr: add address[11:0] and jump to target
RISC-V Instruction Encoding

7-bit function code (additional opcode) 3-bit function code (additional opcode)

First byte read

Destination Reg.
RISC-V: Encoding Schemes

● Integers ● Instructions
○ Unsigned Binary Integers: 0 to +2 – 1
n ○ Encoded as 32-bit instruction words
○ 2s-Complement Signed Integers: –2n - 1 to +2n - 1 – 1 ■ Easier to read in Hexadecimal
○ Memory is byte addressed
■ Sign Extension on load
○ Each address identifies an 8-bit byte
● lb: sign-extend loaded byte ○ RISC-V is Little Endian
● lbu: zero-extend loaded byte ■ Least-significant byte at least
● Float Point: IEEE 754 address of a word
○ RISC-V does not require words to be
○ FP (4 Bytes), FP Double (8 Bytes), FP Quad (16 Bytes) aligned in memory
○ Regularity!
Questions