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2-8255A Interfacing

The document discusses different methods of parallel data transfer and how to implement handshake data transfer using an 8255A programmable parallel port chip. It describes the internal architecture and operational modes of the 8255A chip including mode 0, mode 1 and mode 2 operations.

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0% found this document useful (0 votes)
41 views61 pages

2-8255A Interfacing

The document discusses different methods of parallel data transfer and how to implement handshake data transfer using an 8255A programmable parallel port chip. It describes the internal architecture and operational modes of the 8255A chip including mode 0, mode 1 and mode 2 operations.

Uploaded by

Fullmetal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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DIGITAL INTERFACING…

11/04/23 1
Programmable Parallel Ports and
Handshake Input/Output
• Most of the available port devices, such as the 8255A
on the SDK-86 board, contain two or three ports
which can be programmed to operate in one of
several different modes

• The different modes allow us to use the devices for


many common types of parallel data transfer

11/04/23 2
Digital Interfacing
Methods of parallel data transfer
 8255A internal block diagram and
system connections
 8255A operational modes and
initialization
 Constructing and sending 8255A
control words. (Refer Text Book 2).

11/04/23 3
Methods of Parallel Data Transfer

11/04/23 4
1. Simple Input and Output

• When we need to get a digital data from a simple


switch, such as a thermostat, into a microprocessor,
all we have to do is connect the switch to an input
port line and read the port

• The thermostat data is always present and ready, so


we can read it at any time

11/04/23 5
• Likewise, when we need to output data to a simple
display device such as an LED, all we have to do is
connect the input of the LED buffer on an output
port pin and output the logic level required to turn
on the light

• The LED is always there and ready, so we can send


data to it at any time

11/04/23 6
2. Simple Strobe I/O

• In many applications, valid data is present on


an external device only at a certain time, so it
must be read in at that time

• An example of this is the ASCII – encoded


keyboard

11/04/23 7
• When a key is pressed, circuitry on the keyboard
sends out the ASCII code for the pressed key on eight
parallel data lines, and then sends out a strobe signal
on another line to indicate that valid data is present
on the 8 data lines

• You can read in data only when a strobe pulse tells


you that the data is valid

11/04/23 8
• For low rates of data transfer, such as from a
keyboard to a microprocessor, a simple strobe
transfer works well

• However, for high-speed data transfer this method


doesn’t work, because there is no signal which tells
the sending device when it is safe to send the next
data byte

11/04/23 9
3. Single-Handshake I/O

MICRO- PORT
PERIPHERAL
PROCESSOR DEVICE
PARALLEL
DATA LINES

STB

ACK

11/04/23 10
• The peripheral outputs some parallel data and sends an
STB signal to the microprocessor

• The microprocessor detects the asserted STB signal on a


polled or interrupt basis and reads in the byte of data

• Then the microprocessor sends an Acknowledgement


signal (ACK) to the peripheral to indicate that the data
has been read and that the peripheral can send the next
byte of data

11/04/23 11
4. Double-Handshake Data Transfer
• The circuit connection is same as before

• The sending device asserts its STB line low to ask


“Are you ready?”

• The receiving system raises its ACK line high to say, “I


am ready”

11/04/23 12
• The peripheral device then sends the byte of data
and raises its STB line high to say, “Here is some valid
data for you”

• After it has read in the data, the receiving system


drops its ACK line low to say, “I have the data, thank
you, and I await your request to send the next byte
of data”

11/04/23 13
Implementing Handshake Data Transfer
• For handshake data transfer, a microprocessor can
determine when it is time to send the next data byte on
a polled or on an interrupt basis

• The interrupt approach is usually used, because it makes


better use of the processor's time

• The 8255A can be programmed to automatically receive


an STB signal from a peripheral, send an interrupt signal
to the processor, and send the ACK signal to the
peripheral at the proper times

11/04/23 14
8255A Internal Block Diagram and
System Connections

11/04/23 15
11/04/23 16
11/04/23 17
• The two groups of I/O pins are named as Group A and
Group B

• Group A contains an 8-bit port A along with a 4-bit port C


upper

• The port A lines are identified by symbols PA0-PA7 while


the port C lines are identified as PC4-PC7. Similarly,
Group B contains an 8-bit port B, containing lines PB0-
PB7 and a 4-bit port C with lower bits PC0- PC3

• The port C upper and port C lower can be used in


combination as an 8-bit port C

11/04/23 18
• All of these ports can function independently either
as Input or as Output ports

• This can be achieved by programming the bits of an


internal register of 8255 called as Control Word
Register ( CWR )

• The 8-bit data bus buffer is controlled by the


Read/Write Control Logic

11/04/23 19
• The read/write control logic manages all of the
internal and external transfers of both data and
control words

• RD, WR, A1, A0 and RESET are the inputs provided by


the microprocessor to the READ/ WRITE control logic
of 8255

11/04/23 20
• PA7-PA0: These are eight port A lines that acts as
either latched output or buffered input lines
depending upon the control word loaded into the
control word register

• PC7-PC4 : Upper nibble of port C lines. They may act


as either output latches or input buffers lines. This
port also can be used for generation of handshake
lines in mode 1 or mode 2

11/04/23 21
• PC3-PC0 : These are the lower port C lines, other details
are the same as PC7-PC4 lines

• PB0-PB7 : These are the eight port B lines which are used
as latched output lines or buffered input lines in the
same way as port A

• RD : This is the input line driven by the microprocessor


and should be low to indicate read operation to 8255

• WR : This is an output line driven by the microprocessor.


A low on this line indicates write operation

11/04/23 22
• CS : This is a chip select line. If this line goes low, it
enables the 8255 to respond to RD and WR signals,
otherwise RD and WR signal are neglected
• (A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs,
control the selection of one of the three ports or the
control word register. They are normally connected to
the least significant bits of the address bus (A0 and A1).
A1 A0 SELECTION

0 0 PORT A

0 1 PORT B

1 0 PORT C

1 1 CONTROL

11/04/23 23
11/04/23 24
• D0-D7 : These are the data bus lines those carry data
or control word to/from the microprocessor

• RESET : A logic high on this line clears the control


word register of 8255. All ports are set as input ports
by default after reset.
• If port lines are initialized as output after a reset, the
port try to output to the output of the device
connected to the port. The possible argument b/n
the two outputs may destroy one or both of them,
therefore all the ports are initialized as input after
reset

11/04/23 25
8255A Operational Modes and
Initialization
• These are two basic modes of operation of 8255. I/O
mode and Bit Set-Reset mode (BSR).

• In I/O mode, the 8255 ports work as programmable I/O


ports, while in BSR mode only port C (PC0-PC7) can be
used to set or reset its individual port bits.

• Under the I/O mode of operation, further there are three


modes of operation of 8255, so as to support different
types of applications, mode 0, mode 1 and mode 2

11/04/23 26
MODE 0
• When you want to use a port for simple I/O without
handshaking, you initialize that port in mode 0.
• Two 8-bit ports ( port A and port B )and two 4-bit ports
(port C upper and lower ) are available. The two 4-bit
ports can be combined and used as a third 8-bit port

• Any port can be used as an input or output port

• The two halves of port C are independent, so one half


can be initialized as input, and the other half initialized
as output

11/04/23 27
Mode 1 – Strobed Input
• Mode 1 operation causes port A and/or port B to
function as latching or strobed input devices

• This allows external data to be stored into the port until


the microprocessor is ready to retrieve it

• Port C is also used in Mode 1 operation, not for data, but


for control or handshaking signals that help operate
either or both port A and port B as strobed input ports

11/04/23 28
• The strobed input port captures data from the port
pins when the strobe (STB) is activated

• The STB signal causes data to be captured in the port


and also activates the IBF (Input Buffer Full) and INTR
(Interrupt Request) signals

• Once the microprocessor, through software (IBF) or


hardware (INTR), notices that data are strobed into
the port, it executes an IN instruction to read the
port

11/04/23 29
• The act of reading the port restores both IBF and
INTR to their inactive states until the next data is
strobed into the port

11/04/23 30
11/04/23 31
Timing Diagram – Mode 1 Strobed Input
11/04/23 32
• Out of 8-bit port C, PC0-PC2 are used to generate
control signals for port B and PC3-PC5 are used to
generate control signals for port A. the lines PC6, PC7
may be used as independent data lines

11/04/23 33
Mode 1 – Strobed Output
• Whenever data are written to a port programmed as
a strobed output port, the OBF (Output Buffer Full)
signal becomes a logic 0 to indicate that data are
present in the port latch

• This signal indicates that data are available to an


external I/O device that removes the data by
strobing the ACK (acknowledge) input to the port

• The ACK signal returns the OBF signal to logic 1,


indicating that the buffer is not full
11/04/23 34
11/04/23 35
11/04/23 36
Timing Diagram - Mode 1 Strobed Output
11/04/23 37
Mode 2 – Bidirectional operation
• In mode 2, which is allowed with group A only, port A
becomes bidirectional, allowing data to be
transmitted and received over the same eight wires

• Bi-directional bused data are useful when interfacing


two computers

11/04/23 38
11/04/23 39
Timing Diagram - Mode 2
11/04/23 40
• To transmit data through the bi-directional bus, the
program first tests the OBF signal to determine
whether the output buffer is empty

• If it is, then data are sent to the output buffer via the
OUT instruction

• As soon as the output circuitry sees a logic 0 on OBF,


it sends back the ACK signal to remove it from the
output buffer

• The ACK sets the OBF bit

11/04/23 41
• The external interface sends the data into the port
using the STB signal

• To receive data through the bi-directional port A bus,


the IBF bit is tested with software to decide if data
have been strobed into the port

• If IBF = 1, then the data are input using the IN


instruction

• When the IN instruction executes, the IBF bit is


cleared and the data in the port are moved into AL

11/04/23 42
11/04/23 43
11/04/23 44
Constructing and Sending
8255A Control Words

11/04/23 45
MODE SET CONTROL WORD
11/04/23 46
BIT SET / RESET CONTROL WORD

11/04/23 47
• To send this control word to the 8255A, load it
into AL, Point DX at the control register
address if DX is not already pointing to there,
and send the control word with the
OUT DX, AL instruction

11/04/23 48
1. Logic Controller
2. 7 Segment Display
3. Stepper Motor
4. DAC
5. KeyPad
6. Elevator

Refer Lab Programs and the theory


explained in the Lab…

11/04/23 49
11/04/23 50
7 segment display
• The port C is used to trigger from high to low
• Each time triggering takes place, the bit is shifted in
D-flipflop.
• When the 32 bit bits are received the data is sent
parallelly to the 7-segment display( serial in parallel
out)
• The port B is used to send the data.
• To maintain the ordering of the data from PB0-PB7
to D)-D&, the data in PB0-PB7 is rotated left and
shifted bit is sent to D flip flop. For each trigger one
bit is sent
11/04/23 51
How to find 7-segment code for given character
or number
• There are two types of display
• Common anode: In order to glow particular
segment of a 7-segment display give 0 (low).
• Common cathode In order to glow particular
segment of a 7-segment display give 1(high).
• Note: in the lab we are using common anode
display

11/04/23 52
11/04/23 53
Stepper motor interface

11/04/23 54
• A-PA0
• B-PA3
• A’- PA2
• B’-PA1
• When current is passed through PA0 the electro magnet is
excited. The needle will point to this electromagnet.
(PA3,PA2,PA1,PA0 are 0001)
• whenever a current is passed through PA3 the electro
magnet is excited. The needle will point to this
electromagnet(PA3).(PA3,PA2,PA1,PA0 are 1000)
• This makes needle to move 900 there by making one
full step.

11/04/23 55
• To make a movement smooth both PA0 and
PA3 are excited so that needle moves by 450
There by making half step. Then PA3 is excited
to make a rotation of 900 (one fullstep).
For one full step of rotation stepper motor shaft
moves by 1.80
To move stepper motor shaft by ɵ0 the number
of moves =
Example: to move stepper motor shaft by 900
the number of moves =90/1.8=50 full steps

11/04/23 56
PA3 PA2 PA1 PA0

0 0 0 1
1 0 0 1
0 0 0 1
1 1 0 0
0 1 0 0
0 1 1 0
0 0 1 0
0 0 1 1
0 0 0 1

11/04/23 57
3*8 Key pad Interface
• PC0,PC1 and PC2 are used as output ports to pass current
• PA0 to PA7 are used as input ports to check which key is
pressed.
• Assume that the user has pressed the key 2.the switch will
connect the line from PC0 to PA2 and there will be a flow of
current through PA2 so the bit PA2 will be 1 and remaining
will be zero
• the logic is to pass current for the first row and check if any
key is pressed there. If PA0-PA7 are 0’s then that indicates
no key is pressed in first row. The current is passed to
second row by making PC1 as high.
• If any key is pressed then any one bit from PA0-PA7 will be
set to one
11/04/23 58
11/04/23 59
Thank You…

11/04/23 60
11/04/23 61

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