EE529 Embedded Systems

Lecture 5:
Interrupts

7-1
 Interrupts
 An interrupt is the automatic transfer of
software execution in response to a
hardware event (trigger) that is
asynchronous with current software
execution.
 external I/O device (like a keyboard or
printer) or
 an internal event (like an op code fault, or a
periodic timer.)
 Occurs when the hardware needs or can
service

7-2
 Interrupt Processing

Hardware Busy Done Busy

Hardware
needs
service
Main
Thread Saves
execution Restores
state execution
Interrupt state
Thread
ISR time
provides
service

7-3
 ARM Cortex-M Interrupts

 Each potential interrupt source has a separate arm bit

 Set for those devices from which it wishes to accept interrupts,
 Deactivate in those devices from which interrupts are not allowed

 Each potential interrupt source has a separate flag bit

 hardware sets the flag when it wishes to request an interrupt
 software clears the flag in ISR to signify it is processing the request
(acknowledgement)

 Interrupt enable conditions in processor:

 Global interrupt enable bit, I, in PRIMASK register
 Priority level, BASEPRI, of allowed interrupts (0 = all interrupts are
allowed)

7-4
 Interrupt Conditions

 Four conditions must be true simultaneously for

an interrupt to occur:
1. Arm: control bit for each possible source is set
2. Enable: interrupts globally enabled (I=0 in PRIMASK)
3. Level: interrupt level must be less than BASEPRI
4. Trigger: hardware action sets source-specific flag
 Interrupt remains pending if trigger is set but
any other condition is not true
 Interrupt serviced once all conditions become true
 Need to acknowledge interrupt
 In ISR, clear trigger flag to acknowledge the servicing of
the interrupt and not to get endless interrupts

7-5
 Interrupt Processing

1. The execution of the main program is suspended

1. the current instruction is finished,
2. suspend execution and push 8 registers (R0-R3, R12,
LR, PC, PSR) on the stack
3. LR set to 0xFFFFFFF9 (indicates interrupt return)
4. IPSR (Interrupt Program Status Register) set to
interrupt number (ISR_NUMBER) that corresponds to
the interrupt source
5. sets PC to ISR address
2. The interrupt service routine (ISR) is executed
 clears the flag that requested the interrupt
 performs necessary operations
 communicates using global variables
3. The main program is resumed when ISR executes BX LR
 pulls the 8 registers from the stack
7-6
Registers

PRIMASK has intr. enable (I) bit

BASEPRI has allowed intr. priority

7-7
Priority Mask Register PRIMASK
Disable interrupts (I=1)

CPSID I

Enable interrupts (I=0)

CPSIE I

MRS R0,PRIMASK
CPSID I

MRS PRIMASK,R0

7-8
 Program Status Register PSR
 Accessed separately (APSR, IPSR, EPSR) or all
at once (PSR)

7-9
Interrupt Program Status Register (ISPR)

1. Each interrupt/exception
source has a unique
ISR_NUMBER in IPSR
2. The vector address =
ISR_NUMBER * 4
3. The processor will find the
ISR address using the
corresponding vector
address

7-10
 Interrupt Context Switch

51

Vector address for GPIO Port 1

address of PORT1_IRQHandler() ISR
Interrupt Number 51 is saved
corresponds to GPIO
Port 1
7-11
Nested Vectored Interrupt Controller
(NVIC)

 Hardware unit within the processor that coordinate

among interrupts from multiple sources
 Define priority level of each interrupt source: NVIC_IPRx
registers (from NVIC_IPR0 - NVIC_IPR34)
 Separate enable flag for each interrupt source: two
NVIC_ISERx registers (from NVIC_ISER0 - NVIC_ISER1)
 Interrupt does not set I bit
 When servicing an interrupt, other interrupts are not
disabled. Higher priority interrupts can interrupt lower
priority ones

8-12
 Nested Vectored Interrupt Controller (NVIC)
Example priority registers for some interrupts
Vector Number IRQ ISR name NVIC priority Priority
address startup_msp432.s bits
0x0000002C 11 -5 SVC_Handler SCB_SHPR2 31 – 29
0x00000038 14 -2 PendSV_Handler SCB_SHPR3 23 – 21
0x0000003C 15 -1 SysTick_Handler SCB_SHPR3 31 – 29
0x00000060 24 8 TA0_0_IRQHandler NVIC_IPR2 7–5
0x00000064 25 9 TA0_N_IRQHandler NVIC_IPR2 15 – 13
0x00000068 26 10 TA1_0_IRQHandler NVIC_IPR2 23 – 21
0x0000006C 27 11 TA1_N_IRQHandler NVIC_IPR2 31 – 29
0x00000070 28 12 TA2_0_IRQHandler NVIC_IPR3 7–5
0x00000074 29 13 TA2_N_IRQHandler NVIC_IPR3 15 – 13
0x00000078 30 14 TA3_0_IRQHandler NVIC_IPR3 23 – 21
0x0000007C 31 15 TA3_N_IRQHandler NVIC_IPR3 31 – 29
0x00000080 32 16 EUSCIA0_IRQHandler NVIC_IPR4 7–5
0x00000084 33 17 EUSCIA1_IRQHandler NVIC_IPR4 15 – 13
0x00000088 34 18 EUSCIA2_IRQHandler NVIC_IPR4 23 – 21
0x0000008C 35 19 EUSCIA3_IRQHandler NVIC_IPR4 31 – 29
0x00000090 36 20 EUSCIB0_IRQHandler NVIC_IPR5 7–5
0x00000094 37 21 EUSCIB1_IRQHandler NVIC_IPR5 15 – 13
0x00000098 38 22 EUSCIB2_IRQHandler NVIC_IPR5 23 – 21
0x0000009C 39 23 EUSCIB3_IRQHandler NVIC_IPR5 31 – 29
0x000000CC 51 35 PORT1_IRQHandler NVIC_IPR8 31 – 29
0x000000D0 52 36 PORT2_IRQHandler NVIC_IPR9 7–5
0x000000D4 53 37 PORT3_IRQHandler NVIC_IPR9 15 – 13
0x000000D8 54 38 PORT4_IRQHandler NVIC_IPR9 23 – 21
0x000000DC 55 39 PORT5_IRQHandler NVIC_IPR9 31 – 29
0x000000E0 56 40 PORT6_IRQHandler NVIC_IPR10 7–5

8-13
 Nested Vectored Interrupt Controller (NVIC)
Example priority registers for some interrupts

 High order three bits of each byte define priority

Address 31 – 29 23 – 21 15 – 13 7–5 Name

0xE000E408 Other TA1 TA1CCTL0 Other TA0 TA0CCTL0 NVIC_IPR2
0xE000E40C Other TA3 TA3CCTL0 Other TA2 TA2CCTL0 NVIC_IPR3
0xE000E410 eUSCI_A3 eUSCI_A2 eUSCI_A1 eUSCI_A0 NVIC_IPR4
0xE000E414 eUSCI_B3 eUSCI_B2 eUSCI_B1 eUSCI_B0 NVIC_IPR5
0xE000E418 Timer32 Comb Timer32 Int2 Timer32 Int1 ADC14 NVIC_IPR6
0xE000E41C DMA Int3 DMA Err RTC C AES256 NVIC_IPR7
0xE000E420 I/O Port P1 DMA Int0 DMA Int1 DMA Int2 NVIC_IPR8
0xE000E424 I/O Port P5 I/O Port P4 I/O Port P3 I/O Port P2 NVIC_IPR9
0xE000ED20 TICK PENDSV -- DEBUG SCB_SHPR3

8-14
NVIC Interrupt Set Enable Registers

 Two Enable registers – NVIC_ISERx

 Each 32-bit register has a single enable bit for
a particular device
 NVIC_ISER0 control the IRQ numbers 0 to 31
(interrupt numbers 16 – 47)
 NVIC_ISER1 control the IRQ numbers 32 to 47
(interrupt numbers 48 – 63)

8-15
 GPIO Interrupt Registers
 Each GPIO port has four interrupt control
and status registers used to process
interrupts on pins

8-16
 Interrupt Initialization
 Things you must do:
 Initialize data structures (counters, pointers)
 Arm (specify a flag may interrupt)
 Configure NVIC
o Enable interrupt (e.g. NVIC_ISER1)
o Set priority (e.g. NVIC_IPR8)
 Enable global Interrupts
o Assembly code CPSIE I
o C code EnableInterrupts();

8-17
Interrupt Service Routine (ISR)

 Things you must do in every interrupt

service routine
 Acknowledge
o clear flag that requested the interrupt
 Communicate via shared global variables

8-18
 Interrupt Events
 Respond to infrequent but important events
 Alarm conditions like low battery power
 Error conditions

 I/O synchronization
 Trigger interrupt when signal on a port changes

 Periodic interrupts
 Generated by the timer at a regular rate
 Systick timer can generate interrupt when it hits zero
 Reload value + frequency determine interrupt rate

8-19
 Synchronization
Main Main
program ISR program
ISR
Flag = 1
Other calculations Flag = 1
0
Flag
0
Flag Other calculations 1
1 Flag = 0
Do important stuff
Flag = 0
Do important stuff

 Semaphore
 One thread sets the flag
 The other thread waits for, and clears
 Use global variable to communicate
8-20
Example (Textbook section 5.4.1.2)

 Toggles LED0 whenever SW2 is pressed

#include <msp.h>

uint16_t ret = 0;

void DisableInterrupts(void){ // Disable interrupts

__asm (" CPSID I\n"
" BX LR\n");
}

void EnableInterrupts(void){ // Enable interrupts

__asm (" CPSIE I\n"
" BX LR\n");
}

void WaitForInterrupt(void){ // Go to low power mode and wait for interrupts

__asm (" WFI\n"
" BX LR\n");
}
8-21
Example (Textbook section 5.4.1.2)
int main(void)
{
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; /* Stop watchdog timer */

P3->DIR |= BIT2; // set P3.2 as output pin to LED0

P4->DIR &= ~BIT4; // set P4.4 as input pin to SW2

P4->IES &= ~BIT4; // reset P4IES.4 to 0 to set a rising-edge-trigger
P4->IFG = 0; // clear all flags to avoid false interrupts
P4->IE |= BIT4; // enable P4.4 to receive interrupt

NVIC->IP[PORT4_IRQn] = 3<<5; // set P4 priority level as 3 (bits 23-21)

// ( or NVIC_SetPriority(PORT4_IRQn, 3);)
NVIC->ISER[1] |= 0x40; // set bit 38 (bit 6) on ISER1 to enable P4
EnableInterrupts(); // globally enable the interrupt

while(1) {}
WaitForInterrupt(); // wait for interrupt to happen...
}

void PORT4_IRQHandler(void)
{
char ret = P4IV; // clear P4IFG register
P3OUT ^= BIT2; // toggle LED0 on & off
} 8-22
 Homework

 Read sections: 5.1, 5.2, 5.3 of the textbook in

order to do lab 3.

8-23