CHAPTER 3: ADDRESSING

MODES
3.1 Data-Addressing Modes
3.1.1 Register Addressing
3.1.2 Immediate Addressing
3.1.3 Direct Data Addressing
3.1.4 Register Indirect Addressing
3.1.5 Base-Plus-Index Addressing
3.1.6 Register Relative Addressing
3.1.7 Base Relative-Plus-Index Addressing
3.1.8 Scaled-Index Addressing
3.1.9 RIP Relative Addressing
3.1.10 Data Structures
3.2 Program Memory-Addressing Modes
3.2.1 Direct Program Memory Addressing
3.2.2 Relative Program Memory Addressing
3.2.3 Indirect Program Memory Addressing
3.3 Stack Memory-Addressing Modes
1 Compiled By: Mr. Abdisa L. AUWC dept of CS
 Addressing Modes
Accessing operands (data) in various ways.
The 8086 memory addressing modes provide flexible
access to memory, allowing you to easily access variables,
arrays, records, pointers, and other complex data types.
The different ways in which the location of an operand is
specified in an instruction is called as Addressing mode. These
generic addressing modes are:
Immediate mode Register mode
 Absolute mode Indirect mode
Index mode Base with index
Base with index and offset Relative mode
Auto-increment mode Auto-decrement
2 modeCompiled By: Mr. Abdisa L. AUWC dept of CS
 Register Mode:
The operand is the contents of the processor register.
The name (address) of the register is given in the instruction.
Like AX, BX,CX and DX register
Registers are used to hold the data.
Memory is not accessed
Source and destination registers must match in size
E.g MOV AX, BX will move the contents of register BX into
register AX.
MOV BX,DX
MOV ES,AX
ADD AL, BH
MOV CL, AX (Error)
3 Compiled By: Mr. Abdisa L. AUWC dept of CS
Immediate Addressing Mode:
This addressing mode means the number that we are
loading is part of the instruction itself, and is not found in
the data memory.
The Source operand is constant.
Can be used to load information to any registers.
Operands come immediately after the opcode.
 e.g. MOV AX, 334 - will load the AX register with the
number 344.
• MOV AX, 2550H
• MOV CX, 625
• MOV BL, 40H

4 Compiled By: Mr. Abdisa L. AUWC dept of CS

 Absolute Mode (Direct Mode):
 The operand is in a memory location.
 The data is in memory.
 The address of the operand is provided in the instruction directly.
 The address is the offset address.
 The physical address can be calculated using the content in the DS
register.
 The address of this location is given explicitly in the instruction. ‘
 E.g1 MOV AX, my_variable - the accumulator AX is loaded with
the contents of my_variable.
• E.g 2 MOV DL, [2400]; move contents of DS:2400H into
DL.

• E.g 3 MOV AL, 99H

• MOV [3518], AL
5 Compiled By: Mr. Abdisa L. AUWC dept of CS
Indirect Addressing
 The address of the memory location is in a register(SI, DI,or BX only).
 The physical address is calculated using the content of DS.
 In an 8086 one of these registers is called BP or base pointer.
 If we load BP with a number, then that number can then be used as
the address of a variable.
 e.g. MOV BP, #344; Load the base pointer with the number
344
 MOV AX, [BP]; Load the AX register with the contents of
the memory location pointed to by BP.
 E.g2.
 MOV CL, [SI] ;move the content of DS:SI into CL
 MOV [DI], AH ; move the content of AH into DS:SI
 MOV [SI], AX ; move the content of AX into memory
; locations DS:SI and DS:SI + 1
6 Compiled By: Mr. Abdisa L. AUWC dept of CS
 There are four forms Register Indirect Addressing Mode on the 8086, best
demonstrated by the following instructions:
 mov al, [bx]
 mov al, [bp]
 mov al, [si]
 mov al, [di]
 As with the x86 [bx] addressing mode, these four addressing modes
reference the byte at the offset found in the bx, bp, si, or di register,
respectively.
 The [bx], [si], and [di] modes use the ds segment by default.
 The [bp] addressing mode uses the stack segment(ss)by default.
 You can use the segment override prefix symbols if you wish to
access data in different segments.
 The following instructions demonstrate the use of these overrides:
mov al, cs:[bx]
mov al, ds:[bp]
mov al, ss:[si]
mov al, es:[di]
Compiled By: Mr. Abdisa L. AUWC dept of CS
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• Intel refers to [bx] and [bp] as base addressing modes and bx
and bp as base registers (in fact, bp stands for base pointer).
• Intel refers to the [si] and [di] addressing modes as indexed
addressing modes (si stands for source index, di stands for
8 destination
Compiled By:index).
Mr. Abdisa L. AUWC dept of CS
 Based Relative Addressing Mode
BX or BP can be used.
Effective address: [BX] + disp, or [BP] + disp
The physical address is calculated using DS for [BX] + disp
and SS for [BP] + disp.
E.g MOV CX, [BX] + 10 ; move DS: BX +10 & DS: BX
+10 + 1
; into CX. PA = DS(s1)+ BX +10
 MOV AL, [BP] + 5 ; PA = SS(s1)+ BX + 5

9 Compiled By: Mr. Abdisa L. AUWC dept of CS

 Index Relative Addressing Mode
Similar to the based relative addressing mode.
DI and SI are used to hold the offset address.
DS is used for calculating physical address .

E.g MOV DX, [SI] + 5 ; PA = DS(s1)+ SI +5

 MOV CL, [DI] + 20 ; DS(s1)+ DI +20

10 Compiled By: Mr. Abdisa L. AUWC dept of CS

 Based Index Addressing Mode
Combine the previous 2 modes.
One base register and one index register are used.
For physical address calculation DS is used for BX ; SS is
used for BP.

E.g. MOV CL, [BX] [DI] +8 ; PA = DS(s1)+BX + DI +8

MOV AH, [BP] [SI] + 29 ; PA = SS(s1)+ BP + SI + 29

11 Compiled By: Mr. Abdisa L. AUWC dept of CS

 The allowable forms for based indexed addressing modes are:
 mov al, [bx][si]
 mov al, [bx][di]
 mov al, [bp][si] and
 mov al, [bp][di]
 Suppose that bx contains 1000h and si contains 880h. Then
the instruction
 mov al,[bx][si
 Would load al from location DS:1880h. Likewise, if bp
contains 1598h and di contains 1004, mov ax,[bp+di] will load
the 16 bits in ax from locations SS:259C and SS:259D.
 The addressing modes that do not involve bp use the data
segment by default.

12 Compiled By: Mr. Abdisa L. AUWC dept of CS

• You substitute di in the figure above to obtain the [bx+di]
addressing mode.

13 Compiled By: Mr. Abdisa L. AUWC dept of CS

 Scaled-Index Addressing
Unique to 80386 - Core2 microprocessors.
 uses two 32-bit registers (a base register and an index register)
to access the memory
 The second register (index) is multiplied by a scaling factor.
 The scaling factor can be 1x, 2x, 4x, 8x
 A scaling factor of is implied and need not be included in the
assembly language instruction (MOV AL,[EBX + ECX]).

14 Compiled By: Mr. Abdisa L. AUWC dept of CS

 RIP Relative Addressing
Uses the 64-bit instruction pointer register in the
64-bit mode to address a linear location in the flat
memory model.
 Inline assembler program available to Visual does
not contain any way of using this mode or any
other 64-bit addressing mode.
The Microsoft Visual does not at present support
developing 64-bit assembly code.

15 Compiled By: Mr. Abdisa L. AUWC dept of CS

 Data Structures

Used to specify how information is stored in

a
memory array.
 a template for data
• The start of a structure is identified with the
STRUC assembly language directive and the
end
with the ENDS statement.
16 Compiled By: Mr. Abdisa L. AUWC dept of CS
 Program Memory-Addressing Modes
 Used with the JMP (jump) and CALL
instructions.
Consist of three distinct forms:
Direct Program Memory Addressing
Relative Program Memory Addressing
Indirect Program Memory Addressing

17 Compiled By: Mr. Abdisa L. AUWC dept of CS

 Direct Program Memory Addressing
Used for all jumps and calls by early microprocessor;
also used in high-level languages, such as BASIC.
GOTO and GOSUB instructions
The microprocessor uses this form, but not as often as
relative and indirect program memory addressing.
 The instructions for direct program memory addressing
store the address with the opcode.
The 5-byte machine language version of a JMP
[10000H] instruction.

18 Compiled By: Mr. Abdisa L. AUWC dept of CS

This JMP instruction loads CS with 1000H and IP
with 0000H to jump to memory location 10000H for
the next instruction.
An intersegment jump is a jump to any memory
location within the entire memory system.
Often called a far jump because it can jump to any
memory location for the next instruction.
 In real mode, any location within the first 1M byte.
 In protected mode operation, the far jump can jump to
any location in the 4G-byte address range in the 80386 -
Core2 microprocessors.

19 Compiled By: Mr. Abdisa L. AUWC dept of CS

The only other instruction using direct program
addressing is the intersegment or far CALL
instruction.
Usually, the name of a memory address, called a
label, refers to the location that is called or jumped
to instead of the actual numeric address.
When using a label with the CALL or JMP
instruction, most assemblers select the best form
of program addressing.

20 Compiled By: Mr. Abdisa L. AUWC dept of CS

 Relative Program Memory Addressing
Not available in all early microprocessors, but it is available to
this family of microprocessors.
The term relative means “relative to the instruction pointer
(IP)”.
The JMP instruction is a 1-byte instruction, with a 1-byte or a
2-byte displacement that adds to the instruction pointer.
 An example A JMP [2] instruction.
This instruction skips over the 2 bytes of memory that follow
the JMP instruction.

21 Compiled By: Mr. Abdisa L. AUWC dept of CS

 Indirect Program Memory Addressing
 The microprocessor allows several forms of program indirect
memory addressing for the JMP and CALL instructions.
In 80386 and above, an extended register can be used to hold the
address or indirect address of a relative JMP or CALL.
 for example, the JMP EAX jumps to the location address
by register EAX .
 If a relative register holds the address, the jump is
considered to be an indirect jump.
 For example, JMP [BX] refers to the memory location within the
data segment at the offset address contained in BX.
 At this offset address is a 16-bit number used as the offset
address in the intrasegment jump.
 This type of jump is sometimes called an indirectindirect or
double-indirect jump
Compiled By: Mr. Abdisa L. AUWC dept of CS
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 Example
A jump table that stores addresses of various programs.
The exact address chosen from the TABLE is determined by
an index stored with the jump instruction.

23 Compiled By: Mr. Abdisa L. AUWC dept of CS

 STACK MEMORY-ADDRESSING MODES
 The stack plays an important role in all microprocessors.
 holds data temporarily and stores return addresses used by
procedures
Stack memory is LIFO (last-in, first-out) memory
 describes the way data are stored and removed from the stack.
• Data are placed on the stack with a PUSH instruction;
removed with a POP instruction.
• Stack memory is maintained by two registers:
 The stack pointer (SP or ESP)
 The stack segment register (SS)
• Whenever a word of data is pushed onto the stack, the
high-order 8 bits are placed in the location addressed by
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SP Compiled
– 1. By: Mr. Abdisa L. AUWC dept of CS
Low-order 8 bits are placed in the location addressed by
 The SP is decremented by 2 so the next word is
stored in the next available stack location.
 The SP/ESP register always points to an area of
memory
located within the stack segment.
In protected mode operation, the SS register holds
a selector that accesses a descriptor for the base
address of the stack segment.
When data are popped from the stack, the low
order 8 bits are removed from the location
addressed by SP.
High-order 8 bits are removed; the SP register is
25 incremented by 2
Compiled By: Mr. Abdisa L. AUWC dept of CS
The PUSH and POP instructions: (a) PUSH BX places the
contents of BX onto the stack; (b) POP CX removes data from
the stack and places them into CX. Both instructions are
shown after execution.

26 Compiled By: Mr. Abdisa L. AUWC dept of CS

 Note that PUSH and POP store or retrieve words of data-never bytes -in
8086 - 80286.
 80386 and above allow words or double words to be transferred to and
from the stack.
 Data may be pushed onto the stack from any 16-bit register or segment
register.
In 80386 and above, from any 32-bit extended register.
 Data may be popped off the stack into any register or any segment
register except CS.
 PUSHA and POPA instructions push or pop all except segment registers,
on the stack.
 Not available on early 8086/8088 processors.
 80386 and above allow extended registers to be pushed or popped.
 64-bit mode for Pentium and Core2 does not contain a PUSHA or POPA
instruction
27 Compiled By: Mr. Abdisa L. AUWC dept of CS