Unit IV : Memory Management

Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013
 UNIT–IV: Memory Management

• Logical & Physical Address Space

• Swapping

• Contiguous Memory Allocation

• Paging and Segmentation techniques

• Segmentation with Paging

• Virtual Memory Management

• Demand Paging

• Page Replacement Algorithms

• Thrashing.

• Engg. Applications – Memory management in Windows, Linux.

Operating System Concepts – 9th Edition 8.2 Silberschatz, Galvin and Gagne ©2013
 Background

 Program must be brought (from disk) into memory and placed

within a process for it to be run

 Main memory and registers are only storage CPU can access directly

 Memory unit only sees a stream of addresses + read requests, or

address + data and write requests

 Register access in one CPU clock (or less)

 Main memory can take many cycles, causing a stall

 Cache sits between main memory and CPU registers

 Protection of memory required to ensure correct operation

Operating System Concepts – 9th Edition 8.3 Silberschatz, Galvin and Gagne ©2013
 Base and Limit Registers
 A pair of base and limit registers define the logical address space
 The base register holds the smallest legal physical memory address.
 The limit register specifies the size of the range.

 CPU must check every memory access generated in user mode to be sure
it is between base and limit for that user

Operating System Concepts – 9th Edition 8.4 Silberschatz, Galvin and Gagne ©2013
 Types of Addresses used in a program

 Symbolic addresses

The addresses used in a source code. The variable names, constants, and instruction
labels are the basic elements of the symbolic address space. E.g. an integer variable
called count.

 Relative addresses

At the time of compilation, a compiler converts symbolic addresses into relative

addresses. E.g. 10 bytes from the start of this module.

 Physical or absolute addresses

The loader generates these addresses at the time when a program is loaded into main
memory.

Operating System Concepts – 9th Edition 8.5 Silberschatz, Galvin and Gagne ©2013
 Hardware Address Protection
• The base and limit registers can be loaded only by the operating system, which uses a

special privileged instruction.

• Since privileged instructions can be executed only in kernel mode, and since only the

operating system executes in kernel mode, only the operating system can load the base
and limit registers.

Operating System Concepts – 9th Edition 8.6 Silberschatz, Galvin and Gagne ©2013
 Address Binding
 Programs on disk, ready to be brought into memory to execute form an
input queue
 Without support, must be loaded into address 0000
 Inconvenient to have first user process physical address always at 0000
 How can it not be?
 Further, addresses represented in different ways at different stages of a
program’s life
 Source code addresses usually symbolic
 Compiled code addresses bind to relocatable addresses
 i.e. “14 bytes from beginning of this module”
 Linker or loader will bind relocatable addresses to absolute addresses
 i.e. 74014
 Each binding maps one address space to another

Operating System Concepts – 9th Edition 8.7 Silberschatz, Galvin and Gagne ©2013
 Binding of Instructions and Data to Memory

 Address binding of instructions and data to memory addresses can happen at three
different stages

 Compile time: If memory location known a priori, absolute code can be

generated; must recompile code if starting location changes

 Load time: Must generate relocatable code if memory location is not known at
compile time

 Execution time: Binding delayed until run time if the process can be moved
during its execution from one memory segment to another

 Need hardware support for address maps (e.g., base and limit registers)

Operating System Concepts – 9th Edition 8.8 Silberschatz, Galvin and Gagne ©2013
 Multistep Processing of a User Program

Operating System Concepts – 9th Edition 8.9 Silberschatz, Galvin and Gagne ©2013
 Logical vs. Physical Address Space

 The concept of a logical address space that is bound to a separate physical

address space is central to proper memory management

 Logical address – generated by the CPU; also referred to as virtual address

 Physical address – address seen by the memory unit

 Logical and physical addresses are the same in compile-time and load-time
address-binding schemes; logical (virtual) and physical addresses differ in
execution-time address-binding scheme

 Logical address space is the set of all logical addresses generated by a program

 Physical address space is the set of all physical addresses generated by a program

Operating System Concepts – 9th Edition 8.10 Silberschatz, Galvin and Gagne ©2013
 Memory-Management Unit (MMU)

 Hardware device that at run time maps virtual to physical address

 Many methods possible, covered in the rest of this chapter

 To start, consider simple scheme where the value in the relocation register is added to
every address generated by a user process at the time it is sent to memory

 Base register now called relocation register

 MS-DOS on Intel 80x86 used 4 relocation registers

 The user program deals with logical addresses; it never sees the real physical addresses

 Execution-time binding occurs when reference is made to location in memory

 Logical address bound to physical addresses

Operating System Concepts – 9th Edition 8.11 Silberschatz, Galvin and Gagne ©2013
 Dynamic relocation using a relocation register

 Routine is not loaded until it is called

 Better memory-space utilization; unused

routine is never loaded

 All routines kept on disk in relocatable load

format

 Useful when large amounts of code are

needed to handle infrequently occurring cases

 No special support from the operating system

is required

 Implemented through program design

 OS can help by providing libraries to

implement dynamic loading

Operating System Concepts – 9th Edition 8.12 Silberschatz, Galvin and Gagne ©2013
 Dynamic Linking
 Static linking – system libraries and program code combined by the loader into the binary program
image

 Dynamic linking –linking postponed until execution time

 Small piece of code, stub, used to locate the appropriate memory-resident library routine

 Stub replaces itself with the address of the routine, and executes the routine

 Operating system checks if routine is in processes’ memory address

 If not in address space, add to address space

 Dynamic linking is particularly useful for libraries

 System also known as shared libraries

 Consider applicability to patching system libraries

 Versioning may be needed

Operating System Concepts – 9th Edition 8.13 Silberschatz, Galvin and Gagne ©2013
 Swapping

 A process can be swapped temporarily out of memory to a backing store, and then
brought back into memory for continued execution

 Total physical memory space of processes can exceed physical memory

 Backing store – fast disk large enough to accommodate copies of all memory images for
all users; must provide direct access to these memory images

 Roll out, roll in – swapping variant used for priority-based scheduling algorithms;
lower-priority process is swapped out so higher-priority process can be loaded and
executed

 Major part of swap time is transfer time; total transfer time is directly proportional to the
amount of memory swapped

 System maintains a ready queue of ready-to-run processes which have memory images
on disk

Operating System Concepts – 9th Edition 8.14 Silberschatz, Galvin and Gagne ©2013
 Swapping (Cont.)
 Does the swapped out process need to swap back in to same physical
addresses?

 Depends on address binding method

 Plus consider pending I/O to / from process memory space

 Modified versions of swapping are found on many systems (i.e., UNIX,

Linux, and Windows)

 Swapping normally disabled

 Started if more than threshold amount of memory allocated

 Disabled again once memory demand reduced below threshold

Operating System Concepts – 9th Edition 8.15 Silberschatz, Galvin and Gagne ©2013
 Schematic View of Swapping

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 Swapping
 Say we have Round Robin CPU scheduling and when the time quantum expires the scheduler calls
the dispatcher. The dispatcher checks to see if the next process in the ready queue in in memory. If
not and there is no free memory, the dispatcher swaps out a process currently in memory and swaps
in the desired process from the backing store.

 Backing store – fast disk large enough to accommodate copies of all memory images for all users;
must provide direct access to these memory images

 Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority
process is swapped out so higher-priority process can be loaded and executed

 Major part of swap time is transfer time; total transfer time is directly proportional to the amount of
memory swapped

 Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows)

Operating System Concepts – 9th Edition 8.17 Silberschatz, Galvin and Gagne ©2013
 Drawback of Swapping
 Context switch time is high in swapping.
 E.g. process size = 10 MB and backing store is a hard disk with a transfer rate of 40 MB per second.

 Transfer time = 10 MB / 40 MB/second = ¼ second = 250 milliseconds

 If there is an average latency time of 8 milliseconds. So swap time = 258 milliseconds.

 So total swap time = 258 + 258 = 516 milliseconds

 For efficient CPU utilization we need execution time much larger than swap time, i.e. time quantum
>> 0.516 second

 Swapping is used in few systems. It requires too much swap time and provides too little execution
time to be a reasonable memory management solution.

 In UNIX, swapping is normally disabled. It starts if many processes were running and using a
threshold amount of memory.

Operating System Concepts – 9th Edition 8.18 Silberschatz, Galvin and Gagne ©2013
 Context Switch Time including Swapping

 If next processes to be put on CPU is not in memory, need to swap out a process and swap in
target process

 Context switch time can then be very high

 100MB process swapping to hard disk with transfer rate of 50MB/sec

 Swap out time of 2000 ms

 Plus swap in of same sized process

 Total context switch swapping component time of 4000ms (4 seconds)

 Can reduce if reduce size of memory swapped – by knowing how much memory really
being used

 System calls to inform OS of memory use via request_memory() and release_memory()

Operating System Concepts – 9th Edition 8.19 Silberschatz, Galvin and Gagne ©2013
 Context Switch Time and Swapping (Cont.)

 Other constraints as well on swapping

 Pending I/O – can’t swap out as I/O would occur to wrong process

 Or always transfer I/O to kernel space, then to I/O device

 Known as double buffering, adds overhead

 Standard swapping not used in modern operating systems

 But modified version common

 Swap only when free memory extremely low

Operating System Concepts – 9th Edition 8.20 Silberschatz, Galvin and Gagne ©2013
 Swapping on Mobile Systems
 Not typically supported

 Flash memory based

 Small amount of space

 Limited number of write cycles

 Poor throughput between flash memory and CPU on mobile platform

 Instead use other methods to free memory if low

 iOS asks apps to voluntarily relinquish allocated memory

 Read-only data thrown out and reloaded from flash if needed

 Failure to free can result in termination

 Android terminates apps if low free memory, but first writes application state to flash for fast restart

 Both OSes support paging as discussed below

Operating System Concepts – 9th Edition 8.21 Silberschatz, Galvin and Gagne ©2013
 Contiguous Allocation

 Main memory must support both OS and user processes

 Limited resource, must allocate efficiently

 Contiguous allocation is one early method

 Main memory usually into two partitions:

 Resident operating system, usually held in low memory with

interrupt vector

 User processes then held in high memory

 Each process contained in single contiguous section of memory

Operating System Concepts – 9th Edition 8.22 Silberschatz, Galvin and Gagne ©2013
 Contiguous Allocation (Cont.)

 Relocation registers used to protect user processes from each other, and
from changing operating-system code and data

 Base register contains value of smallest physical address

 Limit register contains range of logical addresses – each logical

address must be less than the limit register

 MMU maps logical address dynamically

 Can then allow actions such as kernel code being transient and
kernel changing size

Operating System Concepts – 9th Edition 8.23 Silberschatz, Galvin and Gagne ©2013
 Hardware Support for Relocation and Limit Registers

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 Multiple-partition allocation
 Multiple-partition allocation

 Degree of multiprogramming limited by number of partitions

 Variable-partition sizes for efficiency (sized to a given process’ needs)

 Hole – block of available memory; holes of various size are scattered throughout memory

 When a process arrives, it is allocated memory from a hole large enough to accommodate it

 Process exiting frees its partition, adjacent free partitions combined

 Operating system maintains information about:

a) allocated partitions b) free partitions (hole)

Operating System Concepts – 9th Edition 8.25 Silberschatz, Galvin and Gagne ©2013
 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?

 First-fit: Allocate the first hole that is big enough

 Best-fit: Allocate the smallest hole that is big enough; must search entire list,
unless ordered by size

 Produces the smallest leftover hole

 Worst-fit: Allocate the largest hole; must also search entire list

 Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed and storage utilization

Operating System Concepts – 9th Edition 8.26 Silberschatz, Galvin and Gagne ©2013
 Fragmentation

 External Fragmentation – total memory space exists to satisfy a request, but

it is not contiguous

 Internal Fragmentation – allocated memory may be slightly larger than

requested memory; this size difference is memory internal to a partition, but
not being used

 First fit analysis reveals that given N blocks allocated, 0.5 N blocks lost to
fragmentation

 1/3 may be unusable -> 50-percent rule

Operating System Concepts – 9th Edition 8.27 Silberschatz, Galvin and Gagne ©2013
 Fragmentation (Cont.)

 Reduce external fragmentation by compaction

 Shuffle memory contents to place all free memory together in

one large block

 Compaction is possible only if relocation is dynamic, and is done

at execution time

 I/O problem

 Latch job in memory while it is involved in I/O

 Do I/O only into OS buffers

 Now consider that backing store has same fragmentation problems

Operating System Concepts – 9th Edition 8.28 Silberschatz, Galvin and Gagne ©2013
 Difference between Paging and Segmentation

Sr No. Paging Segmentation

1 Non-Contiguous memory allocation Non-contiguous memory allocation

2 Paging divides program into fixed size pages. Segmentation divides program into variable size segments.

3 OS is responsible Compiler is responsible.

4 Paging is faster than segmentation Segmentation is slower than paging

5 Paging is closer to Operating System Segmentation is closer to User

6 There is no external fragmentation There is no external fragmentation

7 Logical address is divided into page number and Logical address is divided into segment number and segment
page offset offset

8 Page table is used to maintain the page information. Segment Table maintains the segment information

9 Page table entry has the frame number and some flag Segment table entry has the base address of the segment and
bits to represent details about pages. some protection bits for the segments.

Operating System Concepts – 9th Edition 8.29 Silberschatz, Galvin and Gagne ©2013
 Segmentation
 Memory-management scheme that supports user view of memory
 A program is a collection of segments
 A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays

Operating System Concepts – 9th Edition 8.30 Silberschatz, Galvin and Gagne ©2013
 User’s View of a Program

Operating System Concepts – 9th Edition 8.31 Silberschatz, Galvin and Gagne ©2013
 Logical View of Segmentation

4
1

3 2
4

user space physical memory space

Operating System Concepts – 9th Edition 8.32 Silberschatz, Galvin and Gagne ©2013
 Segmentation Architecture
 Logical address consists of a two tuple:
<segment-number, offset>,

 Segment table – maps two-dimensional physical addresses; each table entry has:
 base – contains the starting physical address where the segments reside in
memory
 limit – specifies the length of the segment

 Segment-table base register (STBR) points to the segment table’s location in

memory

 Segment-table length register (STLR) indicates number of segments used by a

program;
segment number s is legal if s < STLR

Operating System Concepts – 9th Edition 8.33 Silberschatz, Galvin and Gagne ©2013
 Segmentation Architecture (Cont.)

 Protection

 With each entry in segment table associate:

 validation bit = 0  illegal segment

 read/write/execute privileges

 Protection bits associated with segments; code sharing occurs at

segment level

 Since segments vary in length, memory allocation is a dynamic

storage-allocation problem

 A segmentation example is shown in the following diagram

Operating System Concepts – 9th Edition 8.34 Silberschatz, Galvin and Gagne ©2013
 Segmentation Hardware

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 Paging
 Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the
latter is available

 Avoids external fragmentation

 Avoids problem of varying sized memory chunks

 Divide physical memory into fixed-sized blocks called frames

 Size is power of 2, between 512 bytes and 16 Mbytes

 Divide logical memory into blocks of same size called pages

 Keep track of all free frames

 To run a program of size N pages, need to find N free frames and load program

 Set up a page table to translate logical to physical addresses

 Backing store likewise split into pages

 Still have Internal fragmentation

Operating System Concepts – 9th Edition 8.36 Silberschatz, Galvin and Gagne ©2013
 Address Translation Scheme

 Address generated by CPU is divided into:

 Page number (p) – used as an index into a page table which contains base
address of each page in physical memory

 Page offset (d) – combined with base address to define the physical memory
address that is sent to the memory unit

page number page offset

p d
m -n n

 For given logical address space 2m and page size 2n

Operating System Concepts – 9th Edition 8.37 Silberschatz, Galvin and Gagne ©2013
 Paging Hardware

Operating System Concepts – 9th Edition 8.38 Silberschatz, Galvin and Gagne ©2013
 Paging Model of Logical and Physical Memory

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 Paging Example

n=2 and m=4 32-byte memory and 4-byte pages

Operating System Concepts – 9th Edition 8.40 Silberschatz, Galvin and Gagne ©2013
 Paging (Cont.)
 Calculating internal fragmentation
 Page size = 2,048 bytes
 Process size = 72,766 bytes
 35 pages + 1,086 bytes
 Internal fragmentation of 2,048 - 1,086 = 962 bytes
 Worst case fragmentation = 1 frame – 1 byte
 On average fragmentation = 1 / 2 frame size
 So small frame sizes desirable?
 But each page table entry takes memory to track
 Page sizes growing over time
 Solaris supports two page sizes – 8 KB and 4 MB
 Process view and physical memory now very different
 By implementation process can only access its own memory

Operating System Concepts – 9th Edition 8.41 Silberschatz, Galvin and Gagne ©2013
 Free Frames

Before allocation After allocation

Operating System Concepts – 9th Edition 8.42 Silberschatz, Galvin and Gagne ©2013
 Implementation of Page Table

 Page table is kept in main memory

 Page-table base register (PTBR) points to the page table

 Page-table length register (PTLR) indicates size of the page table

 In this scheme every data/instruction access requires two memory

accesses

 One for the page table and one for the data / instruction

 The two memory access problem can be solved by the use of a

special fast-lookup hardware cache called associative memory or
translation look-aside buffers (TLBs)

Operating System Concepts – 9th Edition 8.43 Silberschatz, Galvin and Gagne ©2013
 Paging Hardware With TLB

Operating System Concepts – 9th Edition 8.44 Silberschatz, Galvin and Gagne ©2013
 Implementation of Page Table (Cont.)
 Some TLBs store address-space identifiers (ASIDs) in each
TLB entry – uniquely identifies each process to provide
address-space protection for that process
 Otherwise need to flush at every context switch
 TLBs typically small (64 to 1,024 entries)
 On a TLB miss, value is loaded into the TLB for faster access
next time
 Replacement policies must be considered
 Some entries can be wired down for permanent fast
access

Operating System Concepts – 9th Edition 8.45 Silberschatz, Galvin and Gagne ©2013
 Memory Protection

 Memory protection implemented by associating protection bit with each frame to

indicate if read-only or read-write access is allowed

 Can also add more bits to indicate page execute-only, and so on

 Valid-invalid bit attached to each entry in the page table:

 “valid” indicates that the associated page is in the process’ logical address
space, and is thus a legal page

 “invalid” indicates that the page is not in the process’ logical address space

 Or use page-table length register (PTLR)

 Any violations result in a trap to the kernel

Operating System Concepts – 9th Edition 8.46 Silberschatz, Galvin and Gagne ©2013
 Valid (v) or Invalid (i) Bit In A Page Table

Operating System Concepts – 9th Edition 8.47 Silberschatz, Galvin and Gagne ©2013
 Shared Pages

 Shared code

 One copy of read-only (reentrant) code shared among processes (i.e.,

text editors, compilers, window systems)

 Similar to multiple threads sharing the same process space

 Also useful for interprocess communication if sharing of read-write

pages is allowed

 Private code and data

 Each process keeps a separate copy of the code and data

 The pages for the private code and data can appear anywhere in the
logical address space

Operating System Concepts – 9th Edition 8.48 Silberschatz, Galvin and Gagne ©2013
 Shared Pages Example

Operating System Concepts – 9th Edition 8.49 Silberschatz, Galvin and Gagne ©2013
 Structure of the Page Table
 Memory structures for paging can get huge using straight-forward methods

 Consider a 32-bit logical address space as on modern computers

 Page size of 4 KB (212)

 Page table would have 1 million entries (232 / 212)

 If each entry is 4 bytes -> 4 MB of physical address space / memory for page table
alone

 That amount of memory used to cost a lot

 Don’t want to allocate that contiguously in main memory

 Hierarchical Paging

 Hashed Page Tables

 Inverted Page Tables

Operating System Concepts – 9th Edition 8.50 Silberschatz, Galvin and Gagne ©2013
 Hierarchical Page Tables

 Break up the logical address space into multiple page

tables

 A simple technique is a two-level page table

 We then page the page table

Operating System Concepts – 9th Edition 8.51 Silberschatz, Galvin and Gagne ©2013
 Two-Level Page-Table Scheme

Operating System Concepts – 9th Edition 8.52 Silberschatz, Galvin and Gagne ©2013
 Two-Level Paging Example
 A logical address (on 32-bit machine with 1K page size) is divided into:
 a page number consisting of 22 bits
 a page offset consisting of 10 bits

 Since the page table is paged, the page number is further divided into:
 a 12-bit page number
 a 10-bit page offset
 Thus, a logical address is as follows:

 where p1 is an index into the outer page table, and p2 is the displacement within
the page of the inner page table
 Known as forward-mapped page table

Operating System Concepts – 9th Edition 8.53 Silberschatz, Galvin and Gagne ©2013
 Address-Translation Scheme

Operating System Concepts – 9th Edition 8.54 Silberschatz, Galvin and Gagne ©2013
 64-bit Logical Address Space

 Even two-level paging scheme not sufficient

 If page size is 4 KB (212)
 Then page table has 252 entries
 If two level scheme, inner page tables could be 2 10 4-byte entries
 Address would look like

 Outer page table has 242 entries or 244 bytes

 One solution is to add a 2nd outer page table
 But in the following example the 2nd outer page table is still 234 bytes in size
 And possibly 4 memory access to get to one physical memory location

Operating System Concepts – 9th Edition 8.55 Silberschatz, Galvin and Gagne ©2013
 Three-level Paging Scheme

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 Hashed Page Tables
 Common in address spaces > 32 bits

 The virtual page number is hashed into a page table

 This page table contains a chain of elements hashing to the same location

 Each element contains (1) the virtual page number (2) the value of the mapped page frame (3) a
pointer to the next element

 Virtual page numbers are compared in this chain searching for a match

 If a match is found, the corresponding physical frame is extracted

 Variation for 64-bit addresses is clustered page tables

 Similar to hashed but each entry refers to several pages (such as 16) rather than 1

 Especially useful for sparse address spaces (where memory references are non-contiguous and
scattered)

Operating System Concepts – 9th Edition 8.57 Silberschatz, Galvin and Gagne ©2013
 Hashed Page Table

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 Inverted Page Table

 Rather than each process having a page table and keeping track of all possible logical pages,
track all physical pages

 One entry for each real page of memory

 Entry consists of the virtual address of the page stored in that real memory location, with
information about the process that owns that page

 Decreases memory needed to store each page table, but increases time needed to search the
table when a page reference occurs

 Use hash table to limit the search to one — or at most a few — page-table entries

 TLB can accelerate access

 But how to implement shared memory?

 One mapping of a virtual address to the shared physical address

Operating System Concepts – 9th Edition 8.59 Silberschatz, Galvin and Gagne ©2013
  Virtual Memory (VM)
• Virtual memory –
It’s a technique that allows the execution of processes that are not
completely in memory.

Advantage of using VM:

1. programs can be larger than physical memory.
2. Virtual memory abstracts MM into an extremely large, uniform array of
storage, separating user logical memory from physical memory.

– Only part of the program needs to be in memory for execution

– Logical address space can therefore be much larger than physical address space
– Allows address spaces to be shared by several processes
– Allows for more efficient process creation

• Virtual memory can be implemented via:

– Demand paging
– Demand segmentation

60
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 Virtual Memory That is Larger Than Physical Memory

61
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 Demand Paging
 Bring a page into memory only when it is needed
 Less I/O needed
 Less memory needed
 Faster response
 More users

 Lazy swapper

Never swaps a page into memory unless page will be needed

 Swapper that deals with pages is a pager

62
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 Page Replacement

63
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 Steps in Handling a Page Fault

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 Performance of Demand Paging

 Page Fault Rate 0  p  1.0

 if p = 0 no page faults

 if p = 1, every reference is a fault

 Effective Access Time (EAT)

EAT = (1 – p) x memory access

+ p (page fault overhead

+ swap page out

+ swap page in

+ restart overhead

Operating System Concepts – 9th Edition 8.65 Silberschatz, Galvin and Gagne ©2013
 Performance Example

 Memory access time = 100 nanosec = 10-7

 Page fault overhead = 25 millisec = 0.025

 Page fault rate = 1/1000 = 10-3

 EAT = (1-p) * 10-7 + p * (0.025)

= (0.999) * 10-7 + 10-3 * 0.025

 25 microseconds per reference!

 I.e.,

 250 * memory access time!

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 Demand Paging Example
 Memory access time = 200 nanoseconds

 Average page-fault service time = 8 milliseconds

 EAT = (1 – p) x 200 *10^(-9)+ p (8 milliseconds)

= (1 – p) x 200 + p x 8,000,000

= 200 + p x 7,999,800

 If one access out of 1,000 causes a page fault, then

EAT = 8.2 microseconds.

This is a slowdown by a factor of 40!!

Operating System Concepts – 9th Edition 8.67 Silberschatz, Galvin and Gagne ©2013
 Page Replacement Algorithms
 Want lowest page-fault rate

 Evaluate algorithm by running it on a particular string of memory references (reference

string) and computing the number of page faults on that string

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 Page Replacement Algorithms

• First–In First–Out FIFO

• Optimal
• Least Recently Used (LRU)

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 Page Replacement Algorithms
 Want lowest page-fault rate

 Evaluate algorithm by running it on a particular string of memory references

(reference string) and computing the number of page faults on that string

 In all our examples, the reference string is

 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5

Operating System Concepts – 9th Edition 8.70 Silberschatz, Galvin and Gagne ©2013
 FIFO Page Replacement Algorithm

Reference String: 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 1, 2, 0, 1, 7, 0, 1.

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 Optimal Page Replacement

Reference String: 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 1, 2, 0, 1, 7, 0, 1.

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 LRU Page Replacement

Reference String: 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 1, 2, 0, 1, 7, 0, 1.

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 Thrashing
 If a process does not have “enough” pages, the page-fault rate is very high.
This leads to:
 low CPU utilization
 operating system thinks that it needs to increase the degree of
multiprogramming
 another process added to the system

 Thrashing  a process is busy swapping pages in and out

Operating System Concepts – 9th Edition 8.74 Silberschatz, Galvin and Gagne ©2013
   working-set window  a fixed number of page references Example: 10,000
instruction
 WSSi (working set of Process Pi) =
 total number of pages referenced in the most recent  (varies in time)
 if  too small will not encompass entire locality
 if  too large will encompass several localities
 if  =   will encompass entire program
 D =  WSSi  total demand frames
 if D > m  Thrashing
 Policy if D > m, then suspend one of the processes

Operating System Concepts – 9th Edition 8.75 Silberschatz, Galvin and Gagne ©2013
 Page-Fault Frequency Scheme
 Establish “acceptable” page-fault rate
 If actual rate too low, process loses frame
 If actual rate too high, process gains frame

Operating System Concepts – 9th Edition 8.76 Silberschatz, Galvin and Gagne ©2013
 Translation Lookaside Buffer

 Each virtual memory reference can cause two physical memory accesses

1. One to fetch the page table

2. One to fetch the data

 To overcome this problem a high-speed cache is set up for page table entries

 Called a Translation Lookaside Buffer (TLB)

 Contains page table entries that have been most recently used

Operating System Concepts – 9th Edition 8.77 Silberschatz, Galvin and Gagne ©2013
 Translation Lookaside Buffer

1. Given a virtual address, processor examines the TLB

2. If page table entry is present (TLB hit), the frame number is retrieved and
the real address is formed

3. If page table entry is not found in the TLB (TLB miss), the page number
is used to index the process page table

4. First checks if page is already in main memory

If not in main memory a page fault is issued

5. The TLB is updated to include the new page entry

Operating System Concepts – 9th Edition 8.78 Silberschatz, Galvin and Gagne ©2013
 Use of Translation Lookaside Buffer

Operating System Concepts – 9th Edition 8.79 Silberschatz, Galvin and Gagne ©2013
 Operation of Paging and TLB

Operating System Concepts – 9th Edition 8.80 Silberschatz, Galvin and Gagne ©2013
 Direct Vs. Associative Lookup for Page Table Entries using TLB

Operating System Concepts – 9th Edition 8.81 Silberschatz, Galvin and Gagne ©2013
 Windows
 Uses demand paging with clustering. Clustering brings in pages surrounding the

faulting page

 Processes are assigned working set minimum and working set maximum

 Working set minimum is the minimum number of pages the process is guaranteed

to have in memory

 A process may be assigned as many pages up to its working set maximum

 When the amount of free memory in the system falls below a threshold, automatic

working set trimming is performed to restore the amount of free memory

 Working set trimming removes pages from processes that have pages in excess of

their working set minimum

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 Linux
 Linux address translation
 Linux uses paging to translate virtual addresses to physical addresses
 Linux does not use segmentation
Advantages
 More portable since some RISC architectures don’t support segmentation
 Hierarchical paging is flexible enough
 Intel x86 processes have segments
 Linux tries to avoid using segmentation
 Memory management is simpler when all processes use the same segment register values
 Using segment registers is not portable to other processors
 Linux uses paging 4k page size
 A three-level page table to handle 64-bit addresses
 On x86 processors
 Only a two-level page table is actually used
 Paging is supported in hardware
 TLB is provided as well

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Operating System Concepts – 9th Edition 8.83 Silberschatz, Galvin and Gagne ©2013
 Exam Questions
1.Explain briefly about free space management.

2.Explain the paging concept.

3.What is paging? Why paging is used?

4.Explain Paging technique with example.

5.What is fragmentation? Different types of fragmentation.

6.Explain internal fragmentation.

7.Explain briefly about

a. fragmentation
b. Swapping
c. Thrashing

9.Write short notes on Segmentation.

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 Exam Questions
11. Briefly explain the implementation of virtual memory.

12. Discuss the issues when a page fault occurs.

13. What are the needs for Page replacement algorithms? Explain any two page
replacement algorithms.

14. Write short notes on Page replacement algorithms and its types.

15. Explain the following Page Replacement algorithms.

a. LRU Replacement
b. FIFO Replacement
c. Optimal Replacement
d. Second Chance Replacement

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