Modelling techniques

Different types of Modelling

• Verilog HDL (Hardware Description Language) offers various
modeling techniques that allow engineers to describe digital
hardware at different levels of abstraction.
• Following are the four different levels of abstraction which can
be described by four different coding styles of Verilog language:
1.Behavioral or Algorithmic level
2.Dataflow level
3.Gate level or Structural level
4.Switch level

EC20005 A.Bakshi
Structural / Gate Level Modeling
• The module is implemented in terms of logic gates and interconnections
between these gates. Design at this level is similar to describing a design
in terms of a gate-level logic diagram.
• It provides a textual description of a schematic diagram.
• Verilog recognizes 12 basic gates as predefined primitives.
4 primitive gates of 3-state type.
Other 8 are: and, nand, or, nor, xor, xnor, not, buf
When the gates are simulated, the system assigns a four-valued logic set
to each gate – 0,1,unknown (x) and high impedance (z)
• When a primitive gate is incorporated into a module, we say it is
instantiated in the module.
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 Classification of primitives
Verilog primitives

and / or buf / not Tri-

state

buf bufif0
and not bufif1
nand notif0
or notif1
nor
xor
xnor

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Verilog Logic Gate Primitives
• Verilog supports basic logic gates as predefined primitives.

• These primitives are instantiated like modules except that they are
predefined in Verilog.

• No module definition is needed for using the primitives.

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 Primitive gates
Features:
• 1-output, multiple inputs.
• Output transitions (0, 1, x).

• and i1 (output, input_1, input_2, …, input_n);

• nand i2 (output, input_1, input_2, …, input_n);
• or i3 (output, input_1, input_2, …, input_n);
• nor i4 (output, input_1, input_2, …, input_n);
• xor i5 (output, input_1, input_2, …, input_n);
• xnor i6 (output, input_1, input_2, …, input_n);

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AND / OR PRIMITIVES TRUTH TABLE

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 buf / not primitives
Features:
• 1-input, multiple outputs.
• Output transitions (0, 1, x).

• buf i1 (output_1, output_2, …, output_n, input);

• not i2 (output_1, output_2, …, output_n, input);

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BUF / NOT PRIMITIVES TRUTH TABLE

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Example - Primitive Instantiation
Half Adder

w1

w2

module halfadder (S,C,x,y);

input x,y;
module halfadder (S,C,x,y);
output S,C;
input x,y;
wire w1,w2,xnot,ynot; // internal signal
output S,C;
//Instantiate primitive gates
//Instantiate primitive gates
not n1(xnot,x);
xor x1(S,x,y);
not n2(ynot,y);
and a1(C,x,y);
and a1(w1,x,ynot);
endmodule
and s2(w2,xnot,y);
or o1(S,w1,w2);
and a2( C,x,y);
endmodule EC20005 A.Bakshi
Module Instantiation - Example
module mux2 (a,b,s,y); module mux4 (a,b,c,d,se1, y);
input a,b,s; input a,b,c,d,se1;
output y;
output y;
wire y,s1,w1,w2;
wire y,se1,w1,w2;
not n1(s1,s);
and a1(w1,a,s); mux2 t1(a,b,se1,w1);
and a2 (w2,b,s1); mux2 t2(c,d,se1,w2);
or o1(y,w1,w2); mux2 t3(w1,w2,se1,y);
endmodule
endmodule
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Connecting Ports to External Signals
• There are two methods of making connections between
signals specified in the module instantiation and the ports
in a module definition. These two methods cannot be
mixed.
• Connecting by ordered list
• Connecting ports by name

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Connecting by ordered list
• Connecting by ordered list is the most intuitive method
for most beginners.

• The signals to be connected must appear in the module

instantiation in the same order as the ports in the port list
in the module definition

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Connecting Ports by name
• For large designs where modules have, say, 50 ports,
remembering the order of the ports in the module
definition is impractical and error-prone.

• Verilog provides the capability to connect external signals

to ports by the port names, rather than by position.

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Connecting Ports by name -Example
module twmux (a,b,s,y); module frmux (a,b,c,d,se1, y);
input a,b,s; input a,b,c,d,se1;
output y;
output y;
wire y,s1,w1,w2;
wire y,se1,w1,w2;
not n1(s1,s);
and a1(w1,a,s); twmux t1(.a(a), .b(b), .s(se1), .y(w1) );
and a2 (w2,b,s1); twmux t2(.a (c), .b(d), .s(se1), .y(w2) );
or o1(y,w1,w2); twmux 3(.a(w1), .b(w2), .s(se1), .y(y));
endmodule
endmodule
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EC20005 A.Bakshi
 Dataflow Modeling
• Gate level Modeling approach works well for small circuits but not
for complex designs.

• Designers can design more effectively if they concentrate on

implementing the function at a level of abstraction higher than gate
level.

• Dataflow modeling provides a powerful way to implement a design.

• Verilog allows a circuit to be designed in terms of the data flow

between registers and how a design processes data rather than
instantiation of individual gates.
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Cont’d..
• With gate densities on chips increasing rapidly, dataflow modeling
has assumed great importance.
• Currently, automated tools are used to create a gate-level circuit
from a dataflow design description. This process is called logic
synthesis.
• The data flow modeling allows the designer to concentrate on
optimizing the circuit in terms of data flow.
• In the digital design community, the term RTL (Register Transfer
Level) design is commonly used for a combination of dataflow
modeling and behavioral modeling.
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 Continuous assignment
• This level of abstraction level resembles like that of boolean equation
representation of digital systems.

• The dataflow assignments are called “Continuous Assignments”.

• Continuous assignments are always active.

• Syntax: assign #(delay) target = expression;

• A Verilog module can contain any number of continuous assignment

statements, and all staementsEC20005
executeA.Bakshi
concurrently.
Cont’d..
• LHS target -> always a net, not a register.

• RHS -> registers, nets or function calls.

• Delay values can be specified in terms of time units.

• Whenever an event (change of value) occurs on any operand

used on the RHS of an expression, the expression is evaluated
and assigned to the LHS target.
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Types of continuous assignments
• Regular continuous assignment.

wire mux_out, a_in, b_in, sel_in;

assign mux_out = sel_in ? b_in : a_in;

• Implicit continuous assignment.

wire a_in, b_in, sel_in;

wire mux_out = sel_in ? b_in : a_in;

EC20005 A.Bakshi
 Continuous assignment examples
wire and_out;
assign and_out = i1 & i2; // regular continuous assignment
wire exor_out = i1[31:0] ^ i2[31:0] // implicit assignment

module generate_mux
(a,b,f,s);
a
b
MUX f input a,b;
input s;
s output f;
wire f;
assign f = s? a : b;
endmodule
Note: Conditional Operator generate MUX
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Example – Decoder Inference

module generate decoder

D
(data,select,out); A
DECODER
input data; T
A
input [0:1]select; OUT
output [0:3] out;
wire [0:3] out;
assign out[select]=data;
SELECT
endmodule

Note: Non- constant index in expression on LHS generates DECODER

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Example – ADDER and COMPARATOR

//Dataflow description of 4-bit adder

module binary_adder (A,B,Cin,SUM,Cout);
input [3:0] A,B;
input Cin;
output [3:0] SUM;
output Cout;
assign {Cout,SUM} = A + B + Cin;
endmodule

//Dataflow description of a 4-bit comparator.

module magcomp (A,B,ALTB,AGTB,AEQB);
input [3:0] A,B;
output ALTB,AGTB,AEQB;
assign ALTB = (A < B),
AGTB = (A > B),
AEQB = (A == B);
endmodule
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Behavioral Modeling

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Behavioral or algorithmic level:
• This is the highest level of abstraction provided by Verilog HDL. A
module can be implemented in terms of the desired design algorithm
without concern for the hardware implementation details. Designing at
this level is very similar to C programming.
• It is used mostly to describe sequential circuits, but can also be used to
describe combinational circuits.
• There are two structured procedures in Verilog:
⮚ initial
⮚ always
• Concurrent execution is observed in between these procedures.
• Only registers can be assigned in these procedures.
• The assignments in these procedures are called “procedural assignments”.
• The target output of procedural assignment statements must be of the reg
data type.
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 initial statement
• Starts execution at ‘0’ simulation time and executes only once during the
entire simulation.
• Multiple statements in initial block can be grouped with (begin & end) or
(fork & join) keywords.
• These blocks are not synthesizable.
• initial blocks cannot be nested.
• Each initial block represent a separate and independent activity.
• initial blocks are used in generating test benches.

EC20005 A.Bakshi
 initial block structures
initial
initial begin
xor_out = in1 ^ in2; and_out = a_in & b_in;
end

initial
initial begin
begin clk = 1’b0;
enable = 1’b0; reset = 1’b0;
rst = 1’b0; initial
#100 rst = 1’b1; begin
#20 enable = 1’b1; #100 reset = 1’b1;
end #20 clk = 1’b1;
end
end
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 always statement
• Starts execution at ‘0’ simulation time and is active all through out the
entire simulation.
• Multiple statements inside always block can be grouped with (begin &
end) or (fork & join) keywords.
• Execution of always blocks is controlled by using the timing control.
• always blocks cannot be nested.
• An always block without any sensitivity control will create an infinite loop
and execute forever.
• Each always block represent a separate and independent activity.
• These blocks can synthesize to different hardware depending on their
usage.
• always block with timing control are synthesizable.
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 always block structures
always @(a_in or b_in)
always begin
xor_out = in1 ^ in2; and_out = a_in & b_in;
end

always
always @(posedge reset)
begin
begin
cnt = 1’b0;
if (reset == 1’b1)
reset = 1’b0;
q_out = 1’b0;
always @(posedge clk)
else
begin
q_out = d_in;
#100 cnt = 1’b1;
end
#20 enable = 1’b1;
end
end
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Continuous Vs. procedural assignments

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 Procedural assignments
• These are for updating reg, integer, real, time and their bit /
part selects.
• The values of the variables can get changed only by another
procedural assignment statement.
• Procedural assignments are of two types
• blocking procedural assignment (executed sequentially in the order they
are listed in a sequential block)
• non-blocking procedural assignment (evaluate the expressions on the
right hand side, but do not make the assignment to the left hand side until all
expressions are evaluated)
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 Blocking Assignment
• Most Commonly used type

• The target of assignment gets updated before the next

sequential statement in procedural block is executed.

• A statement using blocking assignment blocks the execution

of the statements following it, until it gets completed.
● B=A
• C=B+1

• Recommended style for modeling combinational logic.(data

dependency)

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 Non-Blocking Assignment
• The assignments to the target gets scheduled for the end of the simulation cycle.

• Normally occurs at the end of the sequential block (begin ….. end)

• Statements subsequent to the instruction under the consideration are not blocked by the
assignment.

• Recommended style for modeling sequential logic

- Can be used to assign several ‘reg’ type variables synchronously, under the control of a
common block
• B <= A
• C <= B + 1

❑A variable cannot appear as the target of both a blocking and a non-blocking assignment.
Following is not permissible
value = value +1;
value <=init; EC20005 A.Bakshi
Procedural timing controls

• Delay based timing control

• Event based timing control

• Level sensitive timing control

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 Delay based timing control
Regular delay control
Format:
#<delay_value> <target> = RHS expression;
• It is used to delay the execution of the corresponding procedural statement by the defined delay
value.
e.g. : #10 c = a + b;
• Intra assignment delay control
Format:
<target> = #<delay_value> RHS expression;
• Intra-assignment delays compute the RHS expression at the current time and defer the
assignment of the computed value to the LHS target by the defined delay value.
e.g. : c = #10 a + b;

• Zero delay control

• Statements with zero delay execute at the end of the current simulation time, when all other
statements in the current simulation timeEC20005
have executed.
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 Event based timing control
• An event is the change in the value on a register or a net.

• Implicit event: The value changes on nets and registers can be used as events to trigger
the execution of a statement.

• The event can also be based on the direction of the change.

• posedge : change towards the value 1

• negedge : change towards the value 0

• Types of event based timing control

⮚ Regular event control

⮚ Event or control

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 Regular event control
Format:
@(event) statement;

e.g.: @ (ena) q = d;

@ (posedge t_in) q = ~q;

@ (negedge clk) q = d;

@ (posedge clk_in) q_out = d_in;

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 Event or control
• The logical or of any number of events can be expressed such that the occurrence of any one of the
events triggers the execution of the procedural statement that follows it.
Format:
always @ (event1 or event2 or event3)
always @ (posedge event1 or negedge event2)
Example-
always @ (in1 or in0 or sel_in)
begin
if (sel_in == 1’b0)
mux_out = in0;
else
mux_out = in1;
end
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 Behavioral constructs
• if-else statements
• The if construct checks a specific condition and decides execution based on the result.
assignment 1;
if(condition) assignment2;
assignment3;
assignment4;
⮚ After execution of assignment1, the condition specified is checked . If it is
satisfied , assignment2 is executed; if not it is skipped.
⮚ In either case the execution continues through assignment3, assignment4, etc.
⮚ Execution of assignment2 alone is dependent on the condition. The rest of the sequence
remains.

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if-else and if-elseif-else statements
if (<expression 1>)
if (<expression>)
begin
begin true_statements 1;
true_statements; end
end :
:
if (<expression>) else if (<expression n>)
begin begin
true_statements; true_statements n;
end end
else else
begin begin
false statements; default_statements;
end end
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Conditional statement - Examples
if (!ena = 1’b1)
if (in1 == 1’b0 && in2 == 1’b0)
begin
dec_o1 = 1’b1;
out = in1 & in2;
end else if (in1 == 1’b0 && in2 == 1’b1)
if (sel == 1’b0) dec_o2 = 1’b1;
begin
mux_out = in0; else if (in1 == 1’b1 && in2 == 1’b0)
end dec_o3 = 1’b1;
else
begin else
mux_out = in1; dec_o4 = 1’b1;
end

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 case statement
case (expression)
•This is a multiway decision
alternative 1:begin
statement that tests whether
an expression matches one of end
a number of other alternatives. alternative 2:begin

end
•Doesn’t treat ‘x’ & ‘z’ as alternative 3:begin
don’t cares.
end
default: begin

end
endcase
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case statement - Example
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
2'd3 : out = i3;
default: $display("Invalid control signals");
endcase
endmodule EC20005 A.Bakshi
Example-Behavioral Modeling
//Behavioral description of 2-to-1-line multiplexer //Behavioral description of 4-to-1 line mux
module mux2x1_bh(A,B,select,OUT);
module mux4x1_bh (i0,i1,i2,i3,select,y);
input A,B,select;
input i0,i1,i2,i3;
output OUT; input [1:0] select;
reg OUT; output y;
always @(select or A or B) reg y;
if (select == 1) always @(i0 or i1 or i2 or i3 or select)
case (select)
OUT = A;
2'b00: y = i0;
else 2'b01: y = i1;
OUT = B; 2'b10: y = i2;
endmodule 2'b11: y = i3;
endcase
endmodule

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Reference

1. Samir Palnitkar,”Verilog HDL: A Guide to Digital Design and Synthesis”

Prentice Hall, Second Edition,2003

Students are encouraged to refer the following website in addition to their

class participation and reading required text and reference books.

⮚http://www.asic-world.com/verilog/

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