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Branch Prediction: Prof. Mikko H. Lipasti University of Wisconsin-Madison

This document discusses branch prediction techniques including: 1. It provides an overview of branch prediction, including target address generation, condition speculation, and using a branch target buffer (BTB) and branch history table (BHT) for prediction. 2. It summarizes two key studies on branch prediction - a 1984 study at UCB that analyzed branch types and prediction accuracy based on opcode vs history, and a 1992 IBM study that analyzed branch instruction distribution and optimal 2-bit predictor designs. 3. It describes the branch prediction implementation in the PowerPC 604 which uses a 64-entry fully associative BTAC for target prediction and a 512-entry direct mapped BHT using 2-bit saturating counters

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68 views

Branch Prediction: Prof. Mikko H. Lipasti University of Wisconsin-Madison

This document discusses branch prediction techniques including: 1. It provides an overview of branch prediction, including target address generation, condition speculation, and using a branch target buffer (BTB) and branch history table (BHT) for prediction. 2. It summarizes two key studies on branch prediction - a 1984 study at UCB that analyzed branch types and prediction accuracy based on opcode vs history, and a 1992 IBM study that analyzed branch instruction distribution and optimal 2-bit predictor designs. 3. It describes the branch prediction implementation in the PowerPC 604 which uses a 64-entry fully associative BTAC for target prediction and a 512-entry direct mapped BHT using 2-bit saturating counters

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iamparvez
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© Attribution Non-Commercial (BY-NC)
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Branch Prediction

Prof. Mikko H. Lipasti University of Wisconsin-Madison


Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti

Lecture Overview
Program control flow Branch Prediction
Implicit sequential control flow Disruptions of sequential control flow
Branch instruction processing Branch instruction speculation

Key historical studies on branch prediction

Branch prediction implementation (PPC 604)


BTAC and BHT design Fetch Address Generation

UCB Study [Lee and Smith, 1984] IBM Study [Nair, 1992]

Program Control Flow


Implicit Sequential Control Flow
Static Program Representation
Control Flow Graph (CFG) Nodes = basic blocks Edges = Control flow transfers

Physical Program Layout


Mapping of CFG to linear program memory Implied sequential control flow

Dynamic Program Execution


Traversal of the CFG nodes and edges (e.g. loops) Traversal dictated by branch conditions

Dynamic Control Flow


Deviates from sequential control flow Disrupts sequential fetching Can stall IF stage and reduce I-fetch bandwidth

Program Control Flow


Dynamic traversal of static CFG Mapping CFG to linear memory

Disruption of Sequential Control Flow


Fetch Instruction/Decode Buffer Decode Dispatch Buffer Dispatch

Issue Branch Execute Finish Complete

Reservation Stations

Reorder/ Completion Buffer Store Buffer Retire

Branch Prediction
Target address generation Target Speculation
Access register:
PC, General purpose register, Link register

Perform calculation:

Condition resolution Condition speculation


Access register:
Condition code register, General purpose register

+/- offset, autoincrement, autodecrement

Perform calculation:
Comparison of data register(s)

Target Address Generation


Fetch PCrel. Reg. ind. with offset Reg. ind. Decode Buffer Decode Dispatch Buffer Dispatch Reservation Stations Branch Execute Finish Complete Store Buffer Retire

Issue

Completion Buffer

Condition Resolution
Fetch Decode Buffer CC reg. Decode Dispatch Buffer Dispatch Reservation Stations Branch Execute Finish Complete Store Buffer Retire

GP reg. value comp.

Issue

Completion Buffer

Branch Instruction Speculation


Prediction Spec. target PC(seq.) Branch Predictor Spec. cond. (using a BTB) BTB update (target addr. and history) to I-cache

FA-mux
PC(seq.) = FA (fetch address) Fetch Decode Buffer Decode Dispatch Buffer Dispatch Reservation Stations Branch

Issue

Execute Finish

Completion Buffer

Branch/Jump Target Prediction


0x0348 0101 (NTNT) 0x0612

Branch inst. Information Branch target address for predict. address (most recent)

Branch Target Buffer: small cache in fetch stage Previously executed branches, address, taken history, target(s) Fetch stage compares current FA against BTB If match, use prediction If predict taken, use BTB target When branch executes, BTB is updated Optimization: Size of BTB: increases hit rate Prediction algorithm: increase accuracy of prediction

Branch Prediction: Condition Speculation


1.

Biased Not Taken


Hardware prediction Does not affect ISA Not effective for loops

2.

Software Prediction
Extra bit in each branch instruction
Set to 0 for not taken Set to 1 for taken

Bit set by compiler or user; can use profiling Static prediction, same behavior every time

3.

Prediction based on branch offset


Positive offset: predict not taken Negative offset: predict taken

4.

Prediction based on dynamic history

UCB Study [Lee and Smith, 1984]


Benchmarks used
26 programs (IBM 370, DEC PDP-11, CDC 6400) 6 workloads (4 IBM, 1 DEC, 1 CDC) Used trace-driven simulation

Branch types
Unconditional: always taken or always not taken Subroutine call: always taken Loop control: usually taken Decision: either way, if-then-else Computed goto: always taken, with changing target Supervisor call: always taken Execute: always taken (IBM 370)

IBM1: compiler IBM2: cobol (business app) IBM3: scientific IBM4: supervisor (OS)

T NT

IBM1 IBM2 IBM3 IBM4 DEC CDC Avg 0.640 0.657 0.704 0.540 0.738 0.778 0.676 0.360 0.343 0.296 0.460 0.262 0.222 0.324

Branch Prediction Function


Prediction function F(X1, X2, )
X1 opcode type X2 history

Prediction effectiveness based on opcode only, or history IBM1 66 64 92 93 94 95 95 IBM2 69 64 95 97 97 97 97 IBM3 71 70 87 91 91 92 92 IBM4 55 54 80 83 84 84 84 DEC 80 74 97 98 98 98 98 CDC 78 78 82 91 94 95 96

Opcode only History 0 History 1 History 2 History 3 History 4 History 5

Example Prediction Algorithm


T T TT T T N N TN TN T T N NN N N T NT T

Branch inst. address

Information Branch target for predict. address

Hardware table remembers last 2 branch outcomes

Results:
Workload Accuracy

History of past several branches encoded by FSM Current state used to generate prediction IBM1 93 IBM2 97 IBM3 IBM4 91 83 DEC 98 CDC 91

Other Prediction Algorithms


N T t T N T n N t? t T T TN n? T N T n N N t? N

TN n? T

N T

Combining prediction accuracy with BTB hit rate (86.5% for 128 sets of 4 entries each), branch prediction can provide the net prediction accuracy of approximately 80%. This implies a 520% performance enhancement.

IBM Study [Nair, 1992]


Branch processing on the IBM RS/6000
Separate branch functional unit Five different branch types
b: unconditional branch bl: branch and link (subroutine calls) bc: conditional branch bcr: conditional branch using link register (returns) bcc: conditional branch using count register

Overlap of branch instructions with other instructions


Zero cycle branches

Two causes for branch stalls


Unresolved conditions Branches downstream too close to unresolved branches

Branch Instruction Distribution


% of each branch type Benchmark spice2g6 doduc matrix300 b 7.86 1.00 0.00 bl 0.30 0.94 0.00 bc bcr bcc 12.58 0.32 8.22 1.01 14.50 0.00 % bc with penalty cycles 3 cyc 2 cyc 1 cyc 13.82 3.12 10.14 1.76 0.68 0.22 0.76 2.02 0.20

tomcatv
gcc espresso li eqntott

0.00
2.30 3.61 2.41 0.91

0.00
1.32 0.58 1.92 0.47

6.10

0.00

0.24

0.02

0.01
4.85 0.31 1.37

15.50 1.81 19.85 0.68 14.36 1.91 32.87 0.51

22.46 9.48 37.37 1.77 31.55 3.44 5.01

11.01 0.80

Exhaustive Search for Optimal 2-bit Predictor


There are 220 possible state machines of 2-bit predictors Some machines are uninteresting, pruning them out reduces the number of state machines to 5248 For each benchmark, determine prediction accuracy for all the predictor state machines Find optimal 2-bit predictor for each application

Number of History Bits Needed


Prediction Accuracy (Overall CPI Overhead) Benchmark 3 bit spice2g6 doduc 2 bit 1 bit 0 bit 97.0 (0.009) 97.0 (0.009) 96.2 (0.013) 76.6 (0.031) 94.2 (0.003) 94.3 (0.003) 90.2 (0.004) 69.2 (0.022)

gcc
espresso li eqntott

89.7 (0.025) 89.1 (0.026) 86.0 (0.033) 50.0 (0.128)


89.5 (0.045) 89.1 (0.047) 87.2 (0.054) 58.5 (0.176) 88.3 (0.042) 86.8 (0.048) 82.5 (0.063) 62.4 (0.142) 89.3 (0.028) 87.2 (0.033) 82.9 (0.046) 78.4 (0.049)

Branch history table size: Direct-mapped array of 2k entries Some programs, like gcc, have over 7000 conditional branches In collisions, multiple branches share the same predictor
Constructive and destructive interference Destructive interference

Marginal gains beyond 1K entries (for these programs)

Branch Prediction Implementation (PPC 604)


Prediction Spec. target Branch Predictor Branch Predictor Update FA to I-cache

FA-mux
FA (fetch address) Fetch Decode Buffer Decode Dispatch Buffer Dispatch BRN SFX SFX CFX Reservation Stations LS FPU

Issue Branch Execute

Finish

Completion Buffer

BTAC and BHT Design (PPC 604)


FA-mux
+4 FA FA Branch Target Address Cache (BTAC) BTAC update BHT prediction BTAC prediction
BTAC: - 64 entries - fully associative - hit => predict taken
Issue Branch BHT: - 512 entries Execute - direct mapped - 2-bit saturating counter history based prediction - overrides BTAC prediction Finish Decode Buffer

I-cache

FAR

FA Branch History Table (BHT)

BHT update

Decode
Dispatch Buffer

Dispatch
BRN SFX SFX CFX Reservation Stations LS FPU

Completion Buffer

BTAC and BHT Design (PPC 604)

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