System Tasks and Compiler Directives
System Tasks and Compiler Directives
And Compiler
Directives
System
Tasks
Verilog provides standard system tasks for certain
routine operations.
All system tasks appear in the form $<keyword>.
Operations such as displaying on the screen,
monitoring values of nets, stopping, and finishing
are done by system tasks.
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Displaying Information
Usage: $stop;
Usage: $finish;
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Example:
initial
begin
clock = 0; reset = 1;
#100 $stop;
#900 $finish;
end
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Compiler Directives
Compiler directives specifies how a compiler should
process it inputs.
It controls the compilation of Verilog description.
A directive is effective from the point at which it is
declared to the point where another directive
overrides it.
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Types of Compiler Directives
The most used compiler directives in Verilog are:
`define :The `define directive is used to define text
macros in Verilog
`include :The `include directive allows you to
include entire contents of a Verilog source file in
another Verilog file during compilation.
The other 2 directives being- `ifdef and `timescale.
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Thank You
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