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BCSE205L-Module 2 Division and Floating Point Arithmetic

The document discusses various topics related to computer organization and architecture including modified Booth's algorithm for division, restoring and non-restoring division, floating point number representation and arithmetic based on the IEEE 754 standard, and examples of floating point addition, multiplication and division.

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Taher Kapadia
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0% found this document useful (0 votes)
52 views

BCSE205L-Module 2 Division and Floating Point Arithmetic

The document discusses various topics related to computer organization and architecture including modified Booth's algorithm for division, restoring and non-restoring division, floating point number representation and arithmetic based on the IEEE 754 standard, and examples of floating point addition, multiplication and division.

Uploaded by

Taher Kapadia
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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BCSE205L – Computer

Organization and Architecture


Topics to be covered
Modified Booths Division (restoring and non-
restoring) - Algorithms for floating point
arithmetic operations
Modified Booth
Algorithm
• Example
• 20 X - 24
20 X -24 using Modified Booth Alg
A Q Q-1 Comments 

0000000 101000 0 Initial values


• +20 = 0010100 M register
0000000 001010 0 Q1Q0Q-1=000
• - M = 1101100
Arithmetic Shift Right(2
• +2M = 0101000 times)
• -2M = 1011000 0000000 001010 0 Q1Q0Q-1=100
1011000 (+)     A = A -2M
• 000000 A register 1011000     Arithmetic Shift Right(2
(Accumulator)       times)
• -24 = 101000 Q register 1110110 000010 1
1110110 000010 1 Q1Q0Q-1=101
1101100 (+)     A = A -1M
    Arithmetic Shift Right(2
1100010
    times)
1111000 100000 1

AQ = 1111000 100000 = Result is negative number in 2’s


complement representation 
Answer = - 480
Restoring Division
• An n-bit positive divisor is loaded into register M and an n-bit positive dividend.
is loaded into register Q at the start of the operation.
• Register A is set to 0. After the division is complete, the n-bit quotient is in register
Q and the remainder is in register A.
• The required subtractions are facilitated by using 2’s-complement arithmetic.
• The extra bit position at the left end of both A and M accommodates the sign bit
during subtractions.
Restoring Division
Flow Chart – Restoring Division
Restoring Division
Restoring Division
• Divisor and Dividend are loaded into M and Q
register.
• Register A is initially set to 0 and n = number
of bits in dividend
• After the division process is completed, n-bit
Quotient is in register Q and the remainder is
in A
Restoring Division
• Step involved:
• Step1 : Shift left A and Q left one binary position
• Step 2: Subtract divisor (i.e add 2’s complement of
divisor(M)) from A and place the answer in
A(AA-M)
• Step 3:If the sign bit of A is 1, set q0 to 0 and add
divisor back to A(restore A), otherwise set q0 to 1.
• Step 4: Repeat steps 1, 2 and 3 for n times
•  
• Example
Non Restoring Division
• If A is positive, we shift left and subtract M, that
is, we perform 2A − M.
• If A is negative, we restore it by performing A + M,
and then we shift it left and subtract M. This is
equivalent to performing 2A + M. (i.e.,2(A+M)-M)
• The q0 bit is appropriately set to 0 or 1 after the
correct operation has been performed. We can
summarize this in the following algorithm for non-
restoring division.
Non Restoring Division
Flow chart
• Example
• 17 ÷ 3 using non
Restoring alg
Floating Point Representation
(IEEE 754 Standard)
• a binary floating-point number can be represented by
– A sign for the number
– Some significant bits
– A signed scale factor exponent for an implied base of 2
• The basic IEEE format is a 32-bit representation
• The leftmost bit represents the sign, S, for the number.
• The next 8 bits, E , represent the signed exponent of the scale factor (with
an implied base of 2), and the remaining 23 bits, M , are the fractional
part of the significant bits. The full 24-bit string, B, of significant bits,
called the mantissa, always has a leading 1
• when the binary point is placed to the right of the first significant bit, the
number is said to be normalized
Floating Point Representation
(IEEE 754 Standard)
IEEE 754 Standard (Single Precision)
• Instead of the actual signed exponent, E, the value stored in
the exponent field is an unsigned integer E´ = E + 127.
• This is called the excess-127 format. Thus, E´ is in the range
0 ≤ E´ ≤ 255.
• The end values of this range, 0 and 255, are used to
represent special values.
• Therefore, the range of E´ for normal values is 1 ≤ E´ ≤ 254.
• This means that the actual exponent, E, is in the range −126
≤ E ≤ 127. The use of the excess-127 representation for
exponents simplifies comparison of the relative sizes of two
floating-point numbers.
Floating Point Representation
(IEEE 754 Standard) Double Precision
Double Precision
• The double-precision format has increased exponent
and mantissa ranges.
• The 11-bit excess-1023 exponent E´ has the range 1
≤ E´ ≤ 2046 for normal values, with 0 and 2047 used
to indicate special values, as before.
• Thus, the actual exponent E is in the range −1022 ≤ E
≤ 1023, providing scale factors of 2−1022 to 21023
(approximately 10±308). The 53-bit mantissa
provides a precision equivalent to about 16 decimal
digits
Normalized Value
Why normalized form?
• Simplifies the exchange of data that includes floating-
point numbers
• Simplifies the arithmetic algorithms to know that the
numbers will always be in this form
• Increases the accuracy of the numbers that can be
stored in a word, since each unnecessary leading 0 is
replaced by another significant digit to the right of the
decimal point
Floating Point Arithmetic
• Add/Subtract Rule
1. Choose the number with the smaller exponent
and shift its mantissa right a number of steps equal
to the difference in exponents.
2. Set the exponent of the result equal to the larger
exponent.
3. Perform addition/subtraction on the mantissas
and determine the sign of the result.
4. Normalize the resulting value, if necessary
Floating point addition in Decimal
• Add 2.9400 × 102 to 4.3100 × 104.
• We rewrite 2.9400 × 102 as 0.0294 × 104
• perform addition of the mantissas to get
4.3394 × 104.
Floating Point Binary Representation
• 85.125
• 85 = 1010101
• 0.125 = 001
• 85.125 = 1010101.001
• =1.010101001 x 2^6
• sign = 0
• 1. Single precision:
• biased exponent 127+6=133
• 133 = 10000101
• Normalised mantisaa = 010101001
• we will add 0's to complete the 23 bits
•  
• The IEEE 754 Single precision is:
• =0 10000101 01010100100000000000000
Floating Point Binary Representation
• Double precision:
• 85.125
• 85 = 1010101
• 0.125 = 001
• 85.125 = 1010101.001 =1.010101001 x 2^6
• sign = 0
• biased exponent 1023+6=1029
• 1029 = 10000000101
• Normalised mantisa = 010101001
• we will add 0's to complete the 52 bits
• The IEEE 754 Double precision is: = 0 10000000101
0101010010000000000000000000000000000000000000000000
Example
• Perform the following arithmetic operation using floating
point arithmetic, In each case, show how the numbers would
be stored using IEEE single-precision format
Rounding
Example 2
Multiply Rule
• 1.Add the exponents and subtract 127 to
maintain the excess-127 representation.
• 2.Multiply the mantissas and determine the
sign of the result.
• 3. Normalize the resulting value, if necessary
Multiplication
• Add the biased exponent

• Multiply the mantissas

• Normalise (already normalised)


• Round the result (no change)
• Adjust the sign
Divide Rule
• Subtract the exponents and add 127 to
maintain the excess-127 representation.
• Divide the mantissas and determine the sign
of the result.
• Normalize the resulting value, if necessary.

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