Mitu Sika
Mitu Sika
Input: x(t)
x
Output: y(t) D Q A
State: A
(A(t), B(t)) C Q
Timed “States”
Sequential Circuits 8/4/23 PJF - 6
Example: A parity checker
5. Next-state logic minimization
Assume D flip-flops
Next state = (present state) XOR (present
input)
Mealy
6. Implement the design Output
Moore
Input D Q Input D Q
Output Current
State
Q Q
CLK CLK
A 2x2 Binary Multiplier
The AND gates produce the
partial products
C3 C2 C1 C0
BINARY DIVISION