MICROPROCESSORS

&
MICROCONTROLLERS

Department of Electrical and Electronics Engineering

MVGR COLLEGE OF ENGINEERING
AUTONOMOUS

Presented by
Mrs. K.KrishnaKumari
Asst.Professor
 What, Why & How?

 Evolution of microprocessor & microcontrollers

 Comparison between microprocessor & microcontrollers
Microprocessor:
 Architecture
 Pin description
 Instruction set
 Addressing modes
 Assembler directives
 MASM software
Application: Program
Microcontroller:
 Architecture
 Pin description
 Instruction set
 Keil software
Application: Program
MICROPROCESSOR
 Evolution of Intel Microprocessor

NAME YEAR TRANSISTORS DATA WIDTH CLOCK SPEED

4004 1971 2300 4-bit 740 KHz

8008 1972 5400 8-bit 500kHz
8080 1974 6000 8-bit 2 MHz
8085 1976 6500 8-bit 3 MHz
8086 1978 29,000 16-bit 5 to 10 MHz
8088 1979 29,000 16-bit 5 to 10 MHz
80386 1986 2,75,000 32-bit 16 MHz
80486 1989 12,00,000 32-bit 25 MHz
Pentium 1993 31,00,000 64-bit 66 MHz
Pentium - iv 2000 42,00,000 64-bit 1.5 GHz
Core i-13 2010 781 million 64-bit 3.33 GHz
 COMPARISON BETWEEN
MICROPROCESSOR AND MICROCONTROLLER
Microprocessor

Microcontroller
Microprocessor RAM ROM
TIMER I/O PORT SERIAL
INTERFACE
Microprocessor Microcontroller

Heart of computer system Heart of embedded system

Memory and I/O components have to be Memory, I/O components are inbuilt
connected externally along with processor

The circuit is large The circuit is small

Cannot be used in compact systems and Can be used in compact systems and
hence inefficient hence it is an efficient technique

Cost of the entire system increases Cost of the entire system is low

Due to external components, the entire Since external components are low, total
power consumption is high. Hence it is power consumption is less and can be
not suitable to used with devices running used with devices running on stored
on stored power like batteries power like batteries

Do not have power saving features Have power saving modes

Microprocessor Microcontroller

Since memory and I/O components are Since components are internal, most of
all external, each instruction will need the operations are internal instruction,
external operation, hence it is relatively hence speed is fast
slower

It has less number of registers, hence It has more number of registers, hence
more operations are memory based the programs are easier to write

Microprocessors are based on von Microcontrollers are based on Harvard

Neumann model where program and architecture where program memory and
data are stored in same memory module data memory are separate

Mainly used in personal computers Used in embedded system eg. Washing

machine, MP3 players
 Over view of 8086 MICROPROCESSOR

 First 16-bit general purpose microprocessor

 It is available in 40- pin dual inline package
 ALU and internal registers work with 16 – bit word
 It contains 16- bit data lines
 It Contains 20- bit address lines, it can access 2^20 memory locations. So, it
can interface upto 1 MB memory
 It contains 2 basic units:
Bus Interface Unit (BIU)
Execution Unit (EU)
 It has 3 interrupt pins
 Frequency range 5-10 MHz
 It implemented based on pipelining technique
 MASM (Macro Assembler) software is used to write ALP (Assembly Language
Program) for 8086 microprocessor
Architecture
 Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
Architecture Bus Interface Unit (BIU)

Dedicated Adder to
generate 20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >>

 Bus Interface Unit (BIU)
Architecture
Segment
Registers

8086’s 1-megabyte The 8086 can directly Programs obtain access to

memory is divided address four segments (256 code and data in the
into segments of up to K bytes within the 1 M byte of segments by changing the
64K bytes each. memory) at a particular segment register content
time. to point to the desired
segments.
 Bus Interface Unit (BIU)
Architecture
Segment Code Segment Register
Registers
16-bit

CS contains the base or start of the current code segment; IP

contains the distance or offset from this address to the next
instruction byte to be fetched.

BIU computes the 20-bit physical address by logically shifting

the contents of CS 4-bits to the left and then adding the 16-bit
contents of IP.

That is, all instructions of a program are relative to the contents

of the CS register multiplied by 16 and then offset is added
provided by the IP.
 Architecture Bus Interface Unit (BIU)

Segment Data Segment Register

Registers
16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or Destination Index

(DI) or a 16-bit displacement are used as offset for computing
the 20-bit physical address.
 Bus Interface Unit (BIU)
Architecture
Segment Stack Segment Register
Registers
16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the Stack

Segment (SS) and the Stack Pointer (SP) for stack instructions
such as PUSH and POP.

In based addressing mode, the 20-bit physical stack address is

calculated from the Stack segment (SS) and the Base Pointer
(BP).
 Bus Interface Unit (BIU)
Architecture
Segment Extra Segment Register
Registers
16-bit

Points to the extra segment in which data (in excess of 64K

pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-bit

physical address for the destination.
 Bus Interface Unit (BIU)
Architecture
Segment Instruction Pointer
Registers
16-bit

Always points to the next instruction to be executed

within the currently executing code segment.

So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64Kb of the code
segment area.

Its content is automatically incremented as the execution

of the next instruction takes place.
Architecture Bus Interface Unit (BIU)

Instruction queue

A group of First-In-First-
Out (FIFO) in which up to 6
bytes of instruction code
are pre fetched from the
memory ahead of time.

This is done in order to

speed up the execution by
overlapping instruction
fetch with execution.

This mechanism is known

as pipelining.
 Execution Unit (EU)
Architecture
EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX 20
can be used as CH and CL
DX can be used as DH and DL
 Execution Unit (EU)
Architecture
EU Accumulator Register (AX)
Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.
 Execution Unit (EU)
Architecture
EU Base Register (BX)
Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.
 Execution Unit (EU)
Architecture
EU Counter Register (CX)
Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.
 Execution Unit (EU)
Architecture
EU Data Register (DX)
Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.

When combined, DL register contains the low order byte of

the word, and DH contains the high-order byte.

Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before a
32 16 division and the 16-bit reminder after division.
 Execution Unit (EU)
Architecture
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack segment in
the external memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.
 Execution Unit (EU)
Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
 Execution Unit (EU)
Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
 Execution Unit (EU)
Architecture
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
28
towards the lowest address, i.e., auto incrementing mode.
8086 MICROPROCESSOR PIN DIAGRAM
Pins & Signals
Common signals

AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals
 Common signals

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the data
bus use BHE (Active Low) signal. It is
multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
 Common signals

TEST

input is tested by the ‘WAIT’ instruction.

8086 will enter a wait state after

execution of the WAIT instruction and
will resume execution only when the is
made low by an active hardware.

This is used to synchronize an external

activity to the processor internal
operation.

READY
This is the acknowledgement from the
slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active high.

 Common signals

RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK
The clock input provides the basic timing
for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled
during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized.
 Min/ Max Pins

The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active
low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.
 Minimum mode signals

Pins 24 -31

For minimum mode operation, the MN/ is tied to

VCC (logic high)

8086 itself generates all the bus control signals

DT/ (Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers

(Data Enable) Output signal from the processor

used as out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

M/ Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever

processor writes data to memory or I/O port

(Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
 Minimum mode signals

Pins 24 -31

For minimum mode operation, the MN/ is tied to

VCC (logic high)

8086 itself generates all the bus control signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.
 Maximum mode signals

During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

,, Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.
 Maximum mode signals

During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

, (Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.
 Maximum mode signals

During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

, (Bus Request/ Bus Grant) These requests are used

by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.

These pins are bidirectional.

The request on will have higher priority than

An output signal activated by the LOCK prefix

instruction.

Remains active until the completion of the

instruction prefixed by LOCK.

The 8086 output low on the pin while executing an

instruction prefixed by LOCK to prevent other bus
masters from gaining control of the system bus.
INSTRUCTION SET
 Instruction Set
8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

 Instruction Set
1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to registers,

memory locations and I/O ports.

Generally involve two operands: Source operand and Destination

operand of the same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory and a 16-
bit data can be moved to 16-bit register/ memory.
 1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)

MOV reg/ mem, data

MOV reg, data (reg)  data

MOV mem, data (mem)  data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)
 1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)

PUSH mem
(SP)  (SP) – 2
MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2

POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2
 1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)

IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)

IN AX, addr8 (AX)  (addr8) OUT addr8, AX (addr8)  (AX)

 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)

ADC reg2, mem (reg2)  (reg2) + (mem)
ADC mem, reg1 (mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16
 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADDC A, data

ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF
 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16
 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF
 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8)  (reg8) + 1

INC reg16 (reg16)  (reg16) + 1

INC mem (mem)  (mem) + 1

DEC reg/ mem

DEC reg8 (reg8)  (reg8) - 1

DEC reg16 (reg16)  (reg16) - 1

DEC mem (mem)  (mem) - 1

 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)
 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder
 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder
 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0
 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0
 2. Arithmetic Instructions

Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0
 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

 3. Logical Instructions

Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

 4. String Manipulation Instructions

 String : Sequence of bytes or words

 8086 instruction set includes instruction for string movement, comparison, scan,
load and store.

 REP instruction prefix : used to repeat execution of string instructions

 String instructions end with S or SB or SW. S represents

string, SB string byte and SW string word.

 Offset or effective address of the source operand is stored in SI register and that of
the destination operand is stored in DI register.

 Depending on the status of DF, SI and DI registers are automatically updated.

 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

 4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP

REPZ/ REPE While CX  0 and ZF = 1, repeat execution of string

instruction and
(Repeat CMPS or SCAS until ZF (CX)  (CX) – 1
= 0)

REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of string

instruction and
(Repeat CMPS or SCAS until ZF (CX)  (CX) - 1
= 1)
 4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE)  (MA)

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

MOVSW
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1)  (MA; MA + 1)

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2

If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2
 4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

Modify flags  (MA) - (MAE)

If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

CMPSW If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

For word operation

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2
If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2
 4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Scan (compare) a string byte or word with accumulator
SCAS

SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)

If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2
 4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)

If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1

LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)

If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2
 4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

STOSW
MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1 )  (AX)

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2
 5. Processor Control Instructions

Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor which

shares the address and data bus with the 8086

LOCK Lock bus during next instruction

 6. Control Transfer Instructions

Transfer the control to a specific destination or target instruction

Do not affect flags

 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

ADDRESSING MODES
 Addressing Modes
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted
in an instruction are known75as addressing modes.

1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for I/O
10. Indirect I/O port Addressing ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode

 Group I : Addressing modes for
register and immediate data

1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL)  (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

 Group I : Addressing modes for
register and immediate data

1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL)  08H

8. String Addressing

9. Direct I/O port Addressing

MOV AX, 0A9FH

10. Indirect I/O port Addressing The 16-bit data (0A9FH) given in the instruction is
moved to AX register
11. Relative Addressing
(AX)  0A9FH
12. Implied Addressing
 Addressing Modes : Memory Access
20 Address lines  8086 can address up to 220
= 1M bytes of memory

However, the largest register is only 16 bits

Physical Address will have to be calculated Physical

Address : Actual address of a byte in memory. i.e.
the value which goes out onto the address bus.

Memory Address represented in the form –

Seg : Offset (Eg - 89AB:F012)

Each time the processor wants to access memory, it

takes the contents of a segment register, shifts it one
hexadecimal place to the left (same as multiplying by 16 bytes of contiguous
memory
1610), then add the required offset to form the 20- bit
address

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
 Group II : Addressing modes for
memory data

1. Register Addressing
Addressing Modes
2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing  
Example:
7. Based Index Addressing
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
 
9. Direct I/O port Addressing
The square brackets around the 1354H denotes
10. Indirect I/O port Addressing the contents of the memory location. When
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
 Group II : Addressing modes for
memory data

1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
 
7. Based Index Addressing
Example:
8. String Addressing Note : Register/ memory
MOV CX, [BX] enclosed in brackets refer to
9. Direct I/O port Addressing content of register/ memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA +1)
 Group II : Addressing modes for
memory data

1. Register Addressing In Based Addressing, BX or BP is used to hold the

base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS is
7. Based Index Addressing
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
(AH)  (MA + 1)
 Group II : Addressing modes for
memory data

1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String Addressing
MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
FFA2H  A2H (Sign extended)
11. Relative Addressing
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
 Group II : Addressing modes for
memory data

1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH  0AH (Sign extended)
7. Based Index Addressing

8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA
10. Indirect I/O port Addressing (DX)  (MA) or,
11. Relative Addressing
(DL)  (MA)
12. Implied Addressing (DH)  (MA + 1)
 Group II : Addressing modes for
memory data

1. Register Addressing Employed in string operations to operate on string

data.
2. Immediate Addressing
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored
in DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
12. Implied Addressing
(MAE)  (MA)
Note : Effective address of the
Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) + 1
 Group III : Addressing
modes for I/O ports

1. Register Addressing These addressing modes are used to access data

from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.
4. Register Indirect Addressing
Example: IN AL, [09H]
5. Based Addressing
Operations: PORTaddr = 09H
6. Indexed Addressing (AL)  (PORT)

7. Based Index Addressing Content of port with address 09H is

moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing
will specify the name of the register which holds
10. Indirect I/O port Addressing
the port address. In 8086, the 16-bit port address
is stored in the DX register.
11. Relative Addressing
Example: OUT [DX], AX
12. Implied Addressing
Operations: PORTaddr = (DX)
(PORT)  (AX)

Content of AX is moved to port

whose address is specified by DX
register.
 Group IV : Relative
Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing 000AH  0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing
MA = BA + EA
12. Implied Addressing
If ZF = 1, then the program control jumps to
new address calculated above.

If ZF = 0, then next instruction of the

program is executed.
 Group IV : Implied
Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

ASSEMBLE DIRECTIVES
 Assemble Directives

Instructions to the Assembler regarding the program being executed.

Control the generation of machine codes and organization of the

program; but no machine codes are generated for assembler
directives.

Also called ‘pseudo instructions’

Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..
 Assemble Directives
DB
Define Byte
DW
Define a byte type (8-bit) variable
SEGMENT
ENDS
Reserves specific amount of memory locations to
each variable
ASSUME
Range : 00H – FFH for unsigned value;
ORG
END 00H – 7FH for positive value and 80H – FFH
EVEN for negative value
EQU
General form : variable DB value/ values
PROC
FAR Example:
NEAR
LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for the
SHORT variable LIST and each data specified in the instruction
are stored as initial value in the reserved memory location
MACRO
ENDM
 Assemble Directives
DB

DW Define Word

SEGMENT Define a word type (16-bit) variable

ENDS
Reserves two consecutive memory locations to
ASSUME each variable

ORG Range : 0000H – FFFFH for unsigned value;

END 0000H – 7FFFH for positive value and 8000H
EVEN
– FFFFH for negative value
EQU

PROC General form : variable DW value/ values

FAR Example:
NEAR
ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for the
SHORT variable ALIST and each 16-bit data specified in the
instruction is stored in two consecutive memory location.
MACRO
ENDM
 Assemble Directives
DB
SEGMENT : Used to indicate the beginning of a
DW
code/ data/ stack segment
SEGMENT
ENDS : Used to indicate the end of a code/ data/
ENDS
stack segment
ASSUME
General form:
ORG
END Segnam SEGMENT
EVEN …
EQU … Program code
… or
… Data Defining Statements
PROC …
FAR …
NEAR Segnam ENDS
ENDP

SHORT

MACRO User defined name of the

segment
ENDM
 Assemble Directives
DB
Informs the assembler the name of the program/
DW
data segment that should be used for a specific
segment.
SEGMENT
General form:
ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ASSUME

ORG
User defined name of the
END Segment Register
segment
EVEN
EQU

PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are stored
in the segment ACODE and data are
stored in the segment ADATA
SHORT

MACRO
ENDM
 Assemble Directives
DB
ORG (Origin) is used to assign the starting address
DW (Effective address) for a program/ data segment

SEGMENT END is used to terminate a program; statements after

ENDS END will be ignored

ASSUME EVEN : Informs the assembler to store program/ data

segment starting from an even address
EQU (Equate) is used to attach a value to a variable
ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address 1000 H

PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHORT ORG 1200H memory location assigned to A will be 1200 H and
A DB 4CH that of B will be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS
 Assemble Directives
DB
PROC Indicates the beginning of a procedure
DW
ENDP End of procedure
SEGMENT
ENDS FAR Intersegment call

NEAR Intrasegment call

ASSUME
General form
ORG
procname PROC[NEAR/ FAR]
END
EVEN …
Program statements of the
…
EQU … procedure

RET Last statement of the

PROC procedure
ENDP
FAR procname ENDP
NEAR

SHORT User defined name of the

procedure
MACRO
ENDM
 Assemble Directives
DB
Examples:
DW

SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is

ENDS declared as NEAR and so the assembler will code
… the CALL and RET instructions involved in this
… procedure as near call and return
ASSUME …

RET
ORG ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT is
declared as FAR and so the assembler will code
… the CALL and RET instructions involved in this
PROC … procedure as far call and return
ENDP …
FAR RET
NEAR CONVERT ENDP

SHORT

MACRO
ENDM
 Assemble Directives
DB
Reserves one memory location for 8-bit signed
DW displacement in jump instructions
Example:
SEGMENT
ENDS

ASSUME JMP SHORT The directive will reserve one memory

AHEAD location for 8-bit displacement named
AHEAD
ORG
END
EVEN
EQU

PROC
ENDP
FAR
NEAR

SHORT

MACRO
ENDM
 Assemble Directives
DB
MACRO Indicate the beginning of a macro
DW
ENDM End of a macro
SEGMENT
ENDS
General form:
ASSUME macroname MACRO[Arg1, Arg2 ...]
Program
… statements in the
ORG … macro
END …
EVEN
EQU macroname ENDM

PROC
ENDP
FAR User defined name of the
NEAR macro

SHORT

MACRO
ENDM
 Example: ARITHMATIC OPERATIONS

 Aim: To write an Assembly Language Program to perform 8-bit Arithmetic

operations using MASM Software.

 Objective:
Learn to write a program for performing arithmetic operations on two 8-bit
operands and get a clear view on each single step execution

 Software Required:
i. Personal Computer with Windows OS
ii. MASM Software
 PROGRAM FOR 8 BIT
ARITHMATIC OPERATION
dosseg \\ Segmenting the memory in small model i.e, entire code, data and stack
.model small \\ segments within 64KB size
.stack 100h \\ Initializing stack memory at 100h address location in memory
.data \\ Defining data segment
n1 db 82h \\ Starting of the data segment
n2 db 62h Input Data: 82 h =130 d,62h=98 d
sum db ?
carry db ?
diff db ? \\ Assigning variables in specific length
brw db ?
prod dw ?
quot db ?
rem db ? \\ Ending of the data segment
.code \\ Defining code segment
start: \\ Starting of the code segment, here ‘start’ is a label name
mov ax, @data \\ Initializing data segment
mov ds, ax
mov cl,00h \\ Writing the program for doing 8-bit arithmetic operation
mov al,n1
add al,n2
adc cl,00h
movsum,al\\ addition operation
movcarry,cl
mov cl,00h
mov al,n1
sub al,n2 \\ subtraction operation
sbb cl,00h
movdiff,al
movbrw,cl
mov al,n1
mul n2 \\ multiplication operation
movprod,ax
mov al,n1
mov ah,00h
div n2 \\ Division operation
movquot, al
mov rem, ah
mov ah, 4ch
int 21h \\ Interrupt for going back to dos command prompt
end start \\ End of the code segment
end \\ End of the program
 RESULTS

INPUT DATA OUTPUT DATA

n1=82h=130d sum =0E4h = 228d
n2=62h=98d carry = 00h=00d
diff =20h = 32d
brw = 00h=00d
prod =31c4h=12740d
quot = 01h=01h
rem = 14h=20d
 Evolution of Microcontroller

NAME Memory Unit YEAR

Intel 8031 8-bit ROM less 1980
Intel 8051 8-bit ROM 1980
Atmel AT89C1 8-bit ROM 1984
Microchip PIC16C64 8-bit 1985

Motorola 68HC11 8-bit (on chip ADC) 1985

AVR 8-bit 1996

ATMega16 16-bit 1996
ATMega 328 32-bit 1996
Arduino 64-bit 2005
 8051 MICROCONTROLLER

 8051 microcontroller is an 8bit microcontroller

 8bit accumulator, 8bit Register and 8bit ALU
 On chip RAM 128 bites (data memory)
 On chip ROM 4 Kbytes (program memory)
 Two 16bit counter/ timer and a 16 bit dptr(data pointer)
 4 byte bi-directional input/ output port
 Power saving mode (on some derivatives)
 16bit address bus:-it can access 2^16 memory locations:-64kb (65536) each of RAM
and ROM
 It is an inclusion of Boolean processing system, have an ability to allow logic
operations to be carried out on registers and RAM
 UART (this serial communication port makes chip to use simply as a serial
communication interface)
 It has four separate Register set. (Each contains 8 Registers (R0 to R7))
8051 MICROCONTROLLER ARCHITECTURE
8051 MICROCONTROLLER PIN DIAGRAM
 8051 microcontroller
programming model / Register set
8051 INSTRUCTION SET
Thank You