MODELING,SYNTAX AND

PROGRAMMING
 TWO DESIGN METHODOLOGIES

• Top Down: The main module is divided into

sub modules which are further divided into
leaf cells.
• Bottom Up: Collect all the leaf cells available
with us and form the higher level modules,
and reach the main module. (WHAT IF THE
BASIC MODULE IS NOT AVAILABLE WITH US?)
 FOUR LEVELS OF ABSTRACTIONS

• Behavioural/Algorithmic level: Highest level of abstraction. Module can

be designed on desired algorithm without concerning about hardware
implementation.
• Dataflow Level: Module is designed by specifying the data flow.
• Gate Level: Module is implemented in terms of logic gates and
interconnections. Similar to gate logic diagram.
• Switch Level: Module can be implemented using switches, storage nodes
and interconnections between them. Lowest Level of Abstraction.
• NOTE
• MODULES IN VERILOG ARE SIMILAR TO THE CLASSES IN C++
• INSTANCE IN VERILOG ARE SIMILAR TO THE OBJECTS IN C++
 STIMULUS AND DESIGN BLOCK.

• In the first style the stimulus block instantiates the

design block and directly drives the signals in the
design block.
• The second style instantiates both stimulus and
design blocks in top level dummy module. The
stimulus block interacts with the design block only at
through the interface.
• STIMULUS BLOCK IS ALSO CALLED THE TEST BENCH.
 LEXICAL CONVENTIONS
• Whitespaces: \b, \t, \n are used for blank spaces, tabs and newlines.
(WHAT IS THE NEED FOR \b, IF AN ORDINARY SPACE “ “ IS USED?)
• Comments: //Single Line Comment /* Multi Line Comment */
• Operators: j= ~b; //Unary Operator
• j= b && c; //Binary Operator
• j= b? c : d //Ternary Operator
• Number Specification: Sized Unknown Impedance (x) Un-sized High
Impedance(z) Negative Underscore and Question Mark
• Strings: “a / b is a string”
• There are 123 keywords
• There are 22 system tasks and functions
• There are 27 compiler directives
• Escaped Identifiers: They begin with a backslash (\) and end with a white
space or a new line. All the characters between a backslash and a
whitespace are processed literally.
 DATA TYPES:
Value Set:
• Value Level Condition
• 0 Logic Zero, False Condition
• 1 Logic One, True Condition
• X Unknown Logic Value
• Z High Impedance, Floating State

• If two signals of strong1 and weak0 contend, the result is resolved as strong1.
• If two signals of equal strengths contend, the result is X (unknown)
• Nets: They represent the connection between the hardware. In the HDL, we they are
represented as wire. They are one bit values by default, unless explicitly mentioned as
vectors. net is not a keyword. It is a class of data types such as wire, wand, wor, tri,
triand, trior, trireg.
• Registers: They represent data storage elements. They retain values until other value is
retained on them.
• Unlike a net, a register does not need a driver. These registers do not need a clock unlike
the hardware registers. They are used with keyword reg. And its default value is x.
• Vectors: wire or reg can be declared as vectors, if bit width is not specified.
Operations can be performed on selected parts of the vectors.
• Integers: it is a register data type, reg can be used as a general purpose
register but in processes like counting it is more convenient to declare them
as integer.
• Real: real numbers are also a register data type and is declared using the
keyword real.
• Time: Verilog simulation is done w.r.t. simulation time. A special time
register is used to save the simulation time. The width of the time register
data type is implementation-specific but is at least 64 bits. The system
function $time is invoked to get the current simulation time.
• Arrays: Arrays are data types to increase the size of register data type and
can be used to create multidimensional matrices.
• Memories: In most cases when RAMs and ROMs are designed by digital
designers. For Verilog, memories are modelled as one dimensional array of
registers. Each element of the array is known as the element or the word,
which is of more than one bits. And is addressed by a single array index.
• A particular word in the memory is obtained by using the address as a
memory in the subscript.
• Parameters: parameter allows constants to be defined
in Verilog. They cannot be used as variables.
Parameter values for each module instance can be
overridden individually at compile time. Parameter size
and type can also be defined.
• Strings: Strings can be stored in the reg data type. The
width must be large enough to hold the string. If the
width is larger than the size of the string, it fills bits to
the left of the string with ZEROS. If the width is smaller
than the string, it truncates leftmost bits of the string.
 SYSTEM TASKS

• $display: This is the main system task for displaying

values of variables or strings or expressions.
• $monitor: This is used to monitor a signal when its
value changes. $monitoron enables monitoring
whereas $monitoroff disables it.
• $stop: The $stop task puts the simulation in an
interactive mode. This is mainly used for debugging.
The designer can suspend the simulation and examine
the value of the signals.
•  $finish: This terminates the simulation.
 COMPILER DIRECTIVES

• `define: This is similar to #define construct in

C. It defines text macros in Verilog. The
compiler substitutes the text of the macro
whenever it encounters <macro_name>
• ‘include: This is used to include header files or
other Verilog source files which contain global
or commonly used definitions
DATAFLOW MODELING
 CONTINUOUS ASSIGNMENT

• A continuous assignment is the most basic statement in the dataflow modelling. It

is used to drive a value onto a net. The syntax is as given below

countinuous_assign ::= assign [ drive_strength ] [delay3] list of net assignments;

list of net assignments ::= net_assignments { , net_assignments}
net_assignments ::= net_lvalue = expression
• The assignment statements begins with keyword assign.
• The drive strength and delay are optional.
• Things that are to be kept in mind while writing an assign statement are:
• The LHS must always be a scalar or a vector net or a concatenation of both the
nets. It cannot be a scalar or a vector register.
• Continuous assignments are always active. The value is evaluated as soon as there
are changes in the RHS operand.
• The operands on the RHS can be reg or wire.
• Delay value are specified in time units
 Implicit Continuous Assignment
Instead of declaring a net and then assigning a
value to it, Verilog provides a shortcut by which a
value can be placed on the net as soon as the
net is declared.
wire out;
assign out = in1 & in2; //regular continuous
assignments //is same as
wire out = in1 & in2; //implicit continuous
assignments
 Implicit Net Declaration

•  If a signal name is used to the left of continuous

assignment, an implicit net declaration will be inferred
for that signal name.
•  If the net is connected to the module port, the width
of the inferred net will be equal to the that of the
module port.

• wire i1,i2;
• assign out = i1 & i2;
 DELAYS
Regular Assignment Delays
• The first method is to give the delay value after the keyword assign.
• Any change in the value of in1 and/or in2 will result in a delay of 10 time units in the output.
• If in1 and/or in2 change before the 10 time units, the value will not be taken for the process
and will wait for the re-computation.

Implicit Continuos Assignment Delay

• An equivalent method is to use an implicit continuous assignment to specify both a delay
and an assignment on the net.

Net Declaration Delay

• A delay can be specified on a net without putting a continuous assignment on the net. If a
delay is specified on a net out then any value change applied to the net out is delayed
accordingly.

wire out; assign #10 out = in1 & in2; //Regular Assignment Delay
wire #10 out = in1 & in2; //Implicit Continuous Assignment Delay
wire #10 out; assign out = in1 & in2; //Net Declaration Delay
EXPRESSIONS, OPERATORS AND OPERANDS

Expressions are constructs that are formed by combination of operators and

operands to produce a result.
• Operands are constructs that assume any of the data types and participate in
expressions to generate desired results.
• Operators are the constructs that operate on operands to produce desired
result. They can be unary, binary or ternary operators.

TYPES OF OPERATORS
Arithmetic Operators
• Various Arithmetic operators are *(multiply), /(divide), +(addition), -
(subtraction), %(modulo), **(power)
• If any operand bit is “x”, the result of entire expression is “x”.
• ‘+’ and ‘-‘ can operate as unary operators to indicate the sign of the given
number.
Logical Operators
• Logical Operators provided by Verilog are &&(logical AND), || (logical OR) and !(logical Negation).
• If any one bit of the operand is “x”, the result of the entire expression is “x”. It is usually treated by simulators
as false condition.
Relational Operators
• The various relational operators are >(greater than), <(less than), >=(greater than or equal to), <=(less than
or equal to).
• It returns 1 if the argument is true and 0 if false. However, when there is one unknown bit, it results in “x”.
Equality Operators
• There are four equality operators provided by Verilog.
• ==(equal to), !=(not equal to), ===(case equality) and !==(case inequality).
• == and != result in unknown in case of “x” and “z’.
• === and !=== check each and every bit including “x” and “z”.
Bitwise Operators
• Bitwise operators are ~(negation), &(and), !(or), ^(xor), ~^ or ^~(xnor).
• Bitwise operators perform bit by bit operation.
• They take a bit from an operand and perform the operation on the corresponding bit of the other operand.
• The operations on “x” and “z” are shown in the truth table below.
Reduction Operators
• Reduction operators are same as the Bitwise operators except the addition of two new operators ~|(nor) and
~%(nand).
• The only difference between the bitwise and the reduction operators is that the result of reduction operator
is just one bit. (of single and same operand)

• It performs the assigned operation on each of its bits starting from the leftmost bit and produces the final
1bit result.
Shift Operators
• >> (Logical Right): It shifts the number of bits mentioned after the operator in the
right direction, thereby appending the leftmost bits by 0.
• << (Logical Left): It shifts the number of bits mentioned after the operator in the
left direction, thereby appending the rightmost bits by 0.
Concatenation Operator
• This is used to append multiple operands.
• Eg: a=00 b=01 y= {a,b} =>y= 0001
• The operand must be sized. Unsized operands are not allowed because the size is
needed for computation of the size of the result.
• They are expressed as operands between braces with commas separating the
operands.
• Operands can be of any data types.
Replication Operator
• Repetitive concatenation of same number can be expressed by using a replication
constant. This specifies how many times to replicate the number within the
brackets. ( { , }). Eg:y= {4{a}}  y = 00000000
Conditional Operator
•  Conditional Operator is a combination of ?:
•  Condition_expression?(true_expression):(false_expression) condition_expression
is evaluated first, if that is true, true_expression is the result otherwise the result is
the false_expression.
 GATE LEVEL MODELING
• Gate Types
• And / Or Gates
• Buf / Not Gates
• Array of Instances
• Gate Delays
• Rise, Fall and Turn off Delays
• Min / Typ / Max values
• Array instantiations may be a synthesizer dependent.
wire [3:0] out, in1, in2;
// basic array instantiations of nand gate.
nand n_gate[3:0] (out, in1, in2);
// this is equivalent to the following:
nand n_gate0 (out[0], in1[0], in2[0]);
nand n_gate1 (out[1], in1[1], in2[1]);
nand n_gate2 (out[2], in1[2], in2[2]);
nand n_gate3 (out[3], in1[3], in2[3]);
module mux4_to_1_structural (i0, i1, i2, i3, s1, s0,
out);
input i0, i1, i2, i3, s1, s0;
output out;
wire s1n, s0n; // Internal wire
wire y0, y1, y2, y3;
// Gate instantiations
not (s1n, s1); // Create s1n and s0n signals
not (s0n, s0);
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
or (out, y0, y1, y2, y3);
endmodule
 Instantiation of Tristate Buffers

To instantiate tristate buffers

The instance_name is optional
// 2-to-1 mux
module two_to_one_mux_tristate (x, y, s, f);
input x, y, s;
output f;
tri f; // internal declaration
// data selector body
bufif0 b1 (f, x, s);
bufif1 b2 (f, y, s);
endmodule
BEHAVIORAL MODELING
 STRUCTURED PROCEDURES:
initial statement
• An initial block starts at time 0 and executes only once.
• If there are more than one initial blocks, they all begin at the same time (“0”). Each block
independently finishes its execution. They must be grouped between begin and end.
They are mainly used for initialization, monitoring waveforms and other processes that do
not require simulation for more than one time.
• There are various short hand syntaxes. For example, when variables are declared they can
be initialized.
• The combined port/data declaration can also be combined with an initialization.
• They can be initialized while declaring them in the port declaration of the module
statement.

always statement
• For programming level always works as infinite loop, but for hardware designers this can
be used as continuous activity from the power on.
This can be used to generate the clock generator.
PROCEDURAL ASSIGNMENTS
• The Syntax for the procedural assignment is as follows

• assignment ::= variable_lvalue = [ delay_or_event_control ] expression

• The difference between the assignment here and that in dataflow is that in dataflow, the
value of LHS operand changes immediately with the change in the RHS value, whereas in this
case, the value of the LHS operand does not change until another procedural assignment is
observed.
Blocking Assignment
• Blocking assignments are executed in the order in which they are assigned. They follow
sequential flow.
• The ‘=’ operator indicates sequential blocking.

• In the Blocking Assignment Example following things are to be noted.

• All statements x = 0 through reg_b = reg_a are executed sequentially at time = 0. The
statements reg_a[2] = 0 at time = 15
• The statement reg_b[15:13] = {x,y,z} at time = 25. Statement count = count + 1 at time = 25 is
executed last because of delays of 15 and 10 time units in the preceding statements .

• Note that if the RHS as more bits as compared to the LHS, the RHS is truncated to match the
width of the LHS, the MSBs are truncated and LSBs are kept as it is. However, if they have RHS
has fewer bits, zeroes are filled in the vacant places.
Non-Blocking Assignment:
• Nonblocking assignments allow scheduling of assignments without
blocking the execution of the statements in the sequential block.
• ‘<=’ operator indicated Nonblocking assignment
• In the nonblocking assignment example, following things should be
noted.
• All statements x = 0 through reg_b = reg_a are executed sequentially at
time = 0. The statements reg_a[2] = 0 at time = 15. The statement
reg_b[15:13] = {x,y,z} at time = 10. Statement count = count + 1 at time =
0 (without any delay) is executed last despite of delays of 15 and 10 time
units in the preceding statements.
• The nonblocking assingments are used to eliminate the race condition
and in order to understand that, we illustrate the example of SWAP.
TIMING CONTROLS
Delay Based Timing Control.
It is an expression that specifies the time duration between when the statement is
encountered and executed. There are three different types of Delay based timing control.
• Regular Delay Control
• Intra-Assignment Delay Control
• Zero Delay Control

Event-Based Timing Control

• An event is the change in the value of a register or a net. Events can be used to trigger the
execution of a statement or a block of statements. There are four types of event based
timing control
Regular Event Control
Named Event Control: Verilog provides the capability to declare an event and recognize the
occurrence of the event. The event cannot hold any data. A named event can be declared
using the keyword event. The event is triggered by the symbol -> and recognized by ‘@’
Event OR Control (Use of @(*) Operator)
Level-Sensitive Timing Control: Verilog provides ability to wait for certain condition to be
true in order for a block of statement to be executed. The keyword used is wait.
always wait (count_enable) #20 count = count + 1;
In the above example, the value of count_enable is continuously monitored. If it is 0, the
statement is not entered. If it is logical 1, the value of count is incremented after 20 time
units.
CONDITIONAL STATEMENTS:
• The conditional statements are nothing but same as if..else as observed in the C language. //Type
1: if (condition) true_statement; //Type 2:

• if(condition) true_statement; else false_statement;

• //Type 3:
• if(condition1) true_statement1;
• else if (condition2) true_statement2;
• else if (conditionN) true_statementN; else false_statement;
MULTIWAY BRANCHING:
• The nested if-else-if becomes cumbersome if there are too many alternatives. Hence, case
comes to the rescue.
• case, default and endcase are the commonly used keywords for the case syntax.

• case(condition)
• alternative1: statement1;
• alternative2: statement2;
• alternative3: statement3;
• alternativeN: statementN;
• default: default_statement;
• endcase
• The case syntax is self-explanatory.
• It compares 0,1,x or z values in the expression bit by bit.
casex, casez keywords
• casez treats all the z valyes in the case alternatives as don’t cares. All bit positions with z can also be
represented by ? in that postion.
• casex treats all x and z values in the case as don’t cares.
LOOPS
• For and While Loops
• The use of while and for loop in Verilog is same as that in C language. The while loop continues until the
condition in the while statement is not true.
• For loops provides a more compact loops structure, the initialization and increment assignment is included
in the for loop.
Repeat Loop
• The keyword repeat is used in a repeat loop.
• This loop iterates a statement for a fixed number of times. It cannot be used to iterate a general logical
expression.
• A repeat construct must contain a number, which can be a variable, constant or a value. However, if the
number is a constant or a signal value, it is evaluated only when the loop starts and not during the loop
execution.
Forever Loop
• The keyword forever is used to express this loop.
• The loops does not contain any expression and executes forever until $finish is encountered.
• This loop is equivalent to a while loop which always has a true condition.
• The loop can be disables by the use of disable statement.
• This is generally used in conjunction with timing constructs, if they are not the loop runs for infinite
amount of time and no further simulation will happen
SEQUENTIAL BLOCK AND PARALLEL BLOCKS
Types of Blocks
Sequential Blocks
• They keywords begin and end are used to group sentences into sequential block.

• They are processed in the order they are specified.

If a delay or event control is specified, it is relative to the simulation time when the
previous statement in the block completed the execution.
Parallel Blocks
• They are specified by keywords fork and join.
• The statements are processed concurrently.
• Ordering of the statements is controlled by delay or event control assigned to each
statement.
• If delay or even control is assigned it is relative to time the block was entered.
• RACE CONDITION: Race condition comes into picture when two statements that use
same variables are executed at the same time.

• In simulation time, all fork-join statements are executed at once. Different simulators
execute statements in different order. Thus the race condition is a limitation in today’s
simulators.
• Features
NESTING: A sequential and parallel blocks can be nested in the same program.
NAMED BLOCKS: Blocks can be given names local variables can be declared for the
named block. Named blocks are a part of design hierarchy. They can be disabled.
DISABLING NAMED BLOCKS: The disable keyword is used to terminate the
execution of a named block. It is used to handle error conditions, get out of the
loop or control execution of the pieces of code, based on control signal. It is
similar to break in C. The difference is break just comes out of the loop, whereas
disable can disable the entire block.
GENERATE
• Generate statements allow Verilog code to be generated dynamically before the
simulation time begins.
• This is particularly useful when same operation is to be performed for multiple
bits of vector.
• All the instructions are coded within generate – end generate keywords.
• Generated instantiations are one or more of the following types Modules User
Defined Primitives Verilog Gate Primitives Continuous Assignments initial and
always blocks.
• Various data types allowed in a generate statement to support interconnections between
structural elements and/or procedural blocks. net, reg integer, real, time, realtime, event
• Tasks and Functions are allowed within a Generate Scope, but not in a generate loop.
Some module declarations and module items are not permitted in a generate statement are
parameter, local parameter input, output and inout declarations specify blocks.
There are three methods to create generate statements:
Generate Loop
• A generate loop allows one or more of the aforementioned to be instantiated multiple times
using a FOR loop.
• In the above example, before the actual simulation, the code is elaborated to create a flat
representation without the generate block. The elaborated code is simulated.
• Thus generate blocks are a simply a convenient way of replacing multiple repetitive Verilog
blocks.
• genvar is a keyword to declare a variable that is used only to evaluate the generate block.
• Its value can be defined only by the generate loop.
• Two generate loops can be nested, provided they have different genvars.
Generate Conditional
• A generate conditional is just like an if-else-if.

Generate Case
• A generate case is just like a case statement
PROGRAMMING
FLIPFLOPS
COUNTERS
SHIFT REGISTERS
Switch Level Programming
Introduction to Back End Tools