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Fetch Decode Execute Cycle

The Fetch Decode Execute cycle describes the process a CPU follows to execute instructions. It involves fetching the next instruction address from memory into registers, decoding the instruction into opcode and operands, and then executing the instruction by performing arithmetic/logic operations in the ALU or sending it to other parts of the CPU. The status register checks for errors between cycles.

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Noah Berger
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328 views

Fetch Decode Execute Cycle

The Fetch Decode Execute cycle describes the process a CPU follows to execute instructions. It involves fetching the next instruction address from memory into registers, decoding the instruction into opcode and operands, and then executing the instruction by performing arithmetic/logic operations in the ALU or sending it to other parts of the CPU. The status register checks for errors between cycles.

Uploaded by

Noah Berger
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Fetch Decode Execute cycle

Fetch
During the start of the fetch part of the cycle the contents of the program
counter (which holds the address of the next instruction to be registered) is
placed into the memory address register (MAR).

Next the address is sent from the MAR to the main memory, which is then
copied to the memory data register (MDR) The program counter whilst this
happens increases by 1 to indicate for the next instruction to be executed

The content of the MBR is then copied to the Current Instruction Register
(CIR)
Decode
The contents of the CIR is decoded by the
control unit

The instruction is split into the opcode and


operands
Execute
Now the information is decoded it is now able to be executed

Any arithmetic and logical instructions are executed by the ALU

Other instructions will be sent to different parts of the CPU to be executed

Between the end of the execute cycle and the start of the fetch cycle the cycle will be checked
over by the Status register (SR) which will flag any errors.

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