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Paper Reiview 20230626 Minwook

The document discusses several approaches to processing-in-memory (PIM) circuits using different memory technologies like SRAM, DRAM, and ReRAM. It analyzes the advantages and disadvantages of each approach. It specifically focuses on SRAM-based PIM circuits and discusses custom SRAM cell designs that aim to improve issues like area overhead, non-linearity, and reduced throughput. It also discusses the challenges and opportunities of cryogenic PIM and introduces several new PIM architectures like DynaPlasia that use novel triple-mode memory cells and reconfigurable dataflow networks.

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16 views

Paper Reiview 20230626 Minwook

The document discusses several approaches to processing-in-memory (PIM) circuits using different memory technologies like SRAM, DRAM, and ReRAM. It analyzes the advantages and disadvantages of each approach. It specifically focuses on SRAM-based PIM circuits and discusses custom SRAM cell designs that aim to improve issues like area overhead, non-linearity, and reduced throughput. It also discusses the challenges and opportunities of cryogenic PIM and introduces several new PIM architectures like DynaPlasia that use novel triple-mode memory cells and reconfigurable dataflow networks.

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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Processing-in-Memory For semiconductor Device

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Review related Papers


An Overview of Processing-in-Memory Circuits for Artificial Intelli-
gence and Machine Learning

• Overview of SRAM/DRAM/ReRAM based on PIM


• SRAM: compared to other candidates for implementing
PIM(simple operation and mature technology) but the area of
cells is larger than others
• DRAM: High density of Cell
• ReRAM: ReRAM technologies are not mature yet
SRAM PIM
• 1.Analog SRAM-Based Processing-in-Memory
• The conventional 6T SRAM-based PIM’s drawback(Due to the shared
write and read path)->voltage drop in both bitlines
• So, several bit cells are proposed. But The problem of larger area
remains.
• 2.Digital SRAM-Based Processing-in-Memory
• Developed to solve ADC/DAC overhead and PVT variation induced non
linearity .
• However, there is a disadvantage in that the memory density of the unit
cell size decreases due to hardware redundancy by memory and com-
putation.
SRAM-Based Processing-in-
memory(PIM)
• SRAM-Based PIM Cell Designs
• Standard 6Tr SRAM-Based PIM
• conventional embedded cache memory cell single bit data.
• Process a binary MAC operation in memory
• At WL(ON and pulse),Two bitline(BL,BLB) voltage will voltage drop (-∆V)
• Binary multiplication results from each cells in the same
Same column are accumulated and aggregated voltage drop

Accumulation in column
of standard 6T SRAM
CELL
SRAM-Based Processing-in-
memory(PIM)
• Custom SRAM Cells for PIM
• The standard 6T SRAM Cell is reading and writing bit line, and the distur-
bance issue by overwrite
• Recently, 8T Foundry SRAM suggests for decoupling read operation
by adding two NMOS.
• The Foundry 8T SRAM can improve the reading disturbance of the existing
6T SRAM, but the Single-ended method has the disadvantage of not only
noise, accuracy, and stability of but also crucially increasing AREA of bit cells
• To overcome the shortcomings of the single-end method, the differ-
ential method and the 10T hierarchical method that use two com-
plementary signal lines were proposed, but the increase in AREA was
the same.
SRAM-Based Processing-in-
memory(PIM)
• A custom dual 7T SRAM-based PIM with bitlines discharging opera-
tion with dynamic range. But non-linearity of voltage remained.
• So, the charge-domain SRAM-based PIM cells use passive capacitors
for sharing or redistributing charges
• The cell requires two read wordlines (RWL and RWLb), a read bitline (RBL), a
unit capacitor, and three switches .
SRAM-Based Processing-in-
memory(PIM)
• Digital SRAM-based PIM
• To overcome analog nonidealities and data conversion
• Digital PIM Cell composed of standard 6T SRAM cell and a NOR
gate-> bitwise multiplier
SRAM-Based PIM Macro Designs
• 8T SRAM cells for dot-product PIM Operation between 4input and
4weight(bitline-discharging and charge-sharing )
• 8T SRAM with column-wise multiply-and-average (MAV)->dynamic
range of bitline and process variation
• Single-ended voltage-mode->reduction of throughput , conversion
overhead and nonlinearity.
• Differential voltage-mode->nonlinearity issue
• Charge-domain SRAM-Based PIM(capacitive coupling or charge-redistri-
bution)->high efficiency and throughput
• These various recent attempts have focused on improving
the previous tradeoff, rather than on reliability and stabil-
ity
Cryogenic PIM : Challenge & Opportunities
• Cryogenic, which improves faster and more efficiently than at room
temperature, is one of the solutions for scaling transistors. Is PIM an
ideal choice in a cryogenic state(77K target)?
• Wire resistance and cap both decrease-> benefit latency for bit-lines pre-
charge, CMOS Logic, array peripheral faster, more energy efficient.
• Negative: Timing Change
• 8T SRAM pre-charge the read bit line and simultaneously connect the read path
to several cells and simultaneously connect. Therefore, it is important to adjust
the timing of read and write
• Timing of WL is also important for 6TSRAM to share the path of read & write,
but supply voltage and ground voltage are sensitive.at cryogenic temperatures
Cryogenic PIM : Challenge & Opportunities
• Results are shown for latency and energy The energy consumption reported does not
include cooling costs, which can be significant. Cryogenic operation provides a latency
advantage for all technologies due to improvements of the peripheral circuitry.
• In conclusion, it is suitable in cryogenic domain, but it should be possible to lower the
problem of timing and the cost of cooling.
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfig-
urable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource
Switching
• Existing PIM research is not the ultimate PIM, or Process-In-
Memory, but Process-Near-Memory, but DynaPlasia has a
structure in which the processor is c
• 3 Key feature
1. Reconfigurable dataflow network and switchable computing-mem-
ory macro
2. Exploiting Dram cells as the unit capacitor of ADC to reduce ADC
Area overhead
3. A signed-input signed-weight to enable high-density cell design
and increasing energy efficient.
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfig-
urable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource
Switching
• Triple Mode
1. Memory 2.Processor 3. capacitor of ADC
• The global IA LINE GIA and GIAb control
the mode of triple mode cell
• The DynaPlasia is fabricated in
28nm CMOS technology
and occupies 20.25mm2 die area
with 9.6Mb cell capacity
A 6T-SRAM-Based Computing-In-Memory
Architecture using 22nm FD-SOI Device
Study on the Vt Variation of TiN-metal Buried-gate (BG) Cell Transis-
tors in DRAM
Buddy-RAM: Improving the Performance and Efficiency of
Bulk Bitwise Operations Using DRAM

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