PROGRAMMABLE

COMMUNICATION INTERFACE
(8251)
1. 8251 INTRODUCTION
• The 8251 microprocessor is a Universal Synchronous Asynchronous
Universal Transmitter (USART) that acts as a mediator between
microprocessor and peripheral to transmit serial data into parallel
form and vice versa.
• 8251 chip converts the parallel data into a serial stream of bits
suitable for serial transmission. It is also able to receive a serial
stream of bits and convert it into parallel data bytes to be read by a
microprocessor.
1.1 GENERAL FUNCTION

•It takes data serially from peripheral (outside devices) and converts into parallel data.

•After converting the data into parallel form, it transmits it to the CPU.

•Similarly, it receives parallel data from microprocessor and converts it into serial form.

•After converting data into serial form, it transmits it to outside device (peripheral)
1.2 BASIC MODES OF TRANSMISSION
• The basic modes of data transmission are:
a) Simplex
b) Duplex
c) Half Duplex
CONTINUATION
• 1.2.1 Simplex mode
Data is transmitted only in one direction over a single communication channel. For
example, the processor may transmit data for a CRT display unit in this mode.
• 1.2.2. Duplex Mode
In duplex mode, data may be transferred between two trans receivers in both
directions simultaneously.
• 1.2.3. Half Duplex mode
In this mode, data transmission may take place in either direction, but at a time
data may be transmitted only in one direction. A computer may communicate with
a terminal in this mode. It is not possible to transmit data from the computer to
the terminal and terminal to computer simultaneously.
2. 8251 ARCHITECTURE
2.1. 8251 BLOCK DIAGRAM
2.1.1. DATA BUS BUFFER
• It is a tri-stated bidirectional, 8-bit buffer
• it helps in interfacing the internal data bus of 8251 to the system data bus.
• The direction of data transfer ids determined by the RD’ and WR̅
• If RD’ is low data is transferred from internal data bus to D0-D7 pins
• If WR’ is low, data is transferred from D0-D7 to internal data bus.
• The data transmission is possible between 8251 and CPU by the data bus buffer
block depending on the signal given by R/W control logic.
2.1.2. READ/WRITE CONTROL LOGIC
• It controls the overall working by selecting the operation to be done.
• It contains four registers: two 8-bit data buffer registers
• one 16-bit control word register
• One 8-bit status register
• The operation selection depends upon input signals as shown.
2.1.3. MODEM CONTROL
(MODULATOR/DEMODULATOR)
•It is a device converts analog signals to digital signals and vice-versa and helps the
computers to communicate over telephone lines or cable wires.
• The following are active-low pins of Modem.
•DSR - Data Set Ready signal is an input signal.
•DTR -Data terminal Ready is an output signal.
•CTS - It is an input signal which controls the data transmit circuit.
•RTS - It is an output signal which is used to set the status RTS.
MODEM CONTINUATION
•The modem can be connected in two different ways:
a) The terminal to modem connections
•In the terminal to modem connection, the RS232 cable is used to
achieve the connection.
MODEM CONTINUATION
b) Full duplex system connection
Both the terminals are supporting full duplex communication so both
will generate appropriate control signals and check the signals and will
perform the data transfer in both directions.
2.1.4. TRANSMIT BUFFER
•This block is used for parallel to serial converter that receives a parallel byte for conversion into serial signal
and further transmission onto the common channel.

• TXD=1 means transmitter will transmit the data.

2.1.5. TRANSMIT CONTROL
•This block is used to control the data transmission with the help of
following pins:
1. TXRDY - It means transmitter is ready to transmit data character.
2. TXEMPTY – Is an output signal which indicates that TXEMPTY pin has
transmitted all the data characters and transmitter is empty now.
3. TXC – Is an active-low input pin which controls the data transmission
rate of transmitted data.
2.1.6. RECEIVE BUFFER
• This block section acts as a buffer for received data.

• RXD: An input signal which receives the data.

2.1.7. RECEIVE CONTROL
•This block controls the receiving data.
1. RXRDY: An input signal indicates that it is ready to receive the data.
2. RXC: An active-low input signal which controls the data transmission
rate of received data.
3. SYNDET/BD: An input or output terminal. External synchronous
mode-input terminal and asynchronous mode-output terminal.
3. 8251 PIN CONFIGURATION
The 8251 also U.S.A.R.T is a 28 pin DIP and deals only with serial data
communication.
It receives parallel data from CPU and transmits serial data after
conversion to external devices.
It receives parallel data and transmits parallel data to CPU.
3.1 8251 PIN DIAGRAM
• 3.1.1. D0 – D7
This is an 8-bit data bus used to read or write status, command word or
data from or to the 8251A.
• 3.1.2. RD
This active-low input to 8251A is used to inform it that the CPU is
reading either data or status information from its internal registers. This
active-low input to 8251A is used to inform it that the CPU is writing
data or control word to 8251A.
• 3.1.3. C / D (Control Word/Data)
This input pin, together with RD and WR inputs, informs the 8251A that
the word on the data bus is either a data or control word/status
information. If this pin is 1, control / status is on the bus, otherwise
data is on the bus.
CONTINUATION: C/D SELECTION
TABLE
• 3.1.4. WR
This is an active-low chip select input of 825lA. If it is high, no read or write
operation can be carried out on 8251. The data bus is tristated if this pin is high.
• 3.1.5. CLK
This input is used to generate internal device timings and is normally connected
to clock generator output. This input frequency should be at least 30 times
greater than the receiver or transmitter data bit transfer rate.
• 3.1.6. RESET
A high on this input forces the 8251A into an idle state. The device will remain
idle till this input signal again goes low and a new set of control word is written
into it. The minimum required reset pulse width is 6 clock states, for the proper
reset operation.
• 3.1.7. TXC (Transmitter Clock Input)
This transmitter clock input controls the rate at which the character is
to be transmitted. The serial data is shifted out on the successive
negative edge of the TXC.
• 3.1.8. TXD (Transmitted Data Output)
This output pin carries serial stream of the transmitted data bits along
with other information like start bit, stop bits and parity bit, etc.
• 3.1.9. RXC (Receiver Clock Input)
This receiver clock input pin controls the rate at which the character is
to be received.
3.1.10. RXD (Receive Data Input)
This input pin of 8251A receives a composite stream of the data to be
received by 8251 A.
• 3.1.11. RXRDY (Receiver Ready Output)
This output indicates that the 8251A contains a character to be read by
the CPU.
• 3.1.12. DSR - Data Set Ready
This is normally used to check if data set is ready when communicating
with a modem.
• 3.1.13. DTR - Data Terminal Ready
This is used to indicate that the device is ready to accept data when the
8251 is communicating with a modem.
• 3.1.14. RTS - Request to Send Data
This signal is used to communicate with a modem.
• 3.1.15 TXE - Transmitter Empty
The TXE signal can be used to indicate the end of a transmission mode.
4. OPERATING MODES OF 8251
The operating modes of the 8251 are:
• Asynchronous mode
• Synchronous mode
4.1 ASYNCHROUNS MODE
4.1.1. Asynchronous Mode (Transmission)
When a data character is sent to 8251A by the CPU, it adds start bits
prior to the serial data bits, followed by optional parity bit and stop bits
using the asynchronous mode instruction control word format. This
sequence is then transmitted using TXD output pin on the falling edge
of TXC
4.1.2 Asynchronous Mode (Receive)
A falling edge on RXD input line marks a start bit. The receiver requires
only one stop bit to mark end of the data bit string, regardless of the
stop bit programmed at the transmitting end. The 8-bit character is
then loaded into the into parallel I/O buffer of 8251. RXRDY pin is raised
high to indicate to the CPU that a character is ready for it. If the
previous character has not been read by the CPU, the new character
replaces it, and the overrun flag is set indicating that the previous
character is lost.
4.1.3. MODE INSTRUCTION FORMAT
FOR ASYNCHRONOUS MODE
4.1.4. ASYNCHROUNS MODE
TRANSMIT AND RECIEVE
4.2. SYNCHROUS MODE
Synchronous Mode Instruction Format
• 4.2.1. Synchronous Mode (Transmission)
The TXD output is high until the CPU sends a character to 8251 which
usually is a SYNC character. When CTS line goes low, the first character
is serially transmitted out. Characters are shifted out on the falling edge
of TXC .Data is shifted out at the same rate as TXC , over TXD output
line. If the CPU buffer becomes empty, the SYNC character or
characters are inserted in the data stream over TXD output.
• 4.2.2. Synchronous Mode (Receiver)
In this mode, the character synchronization can be achieved internally or
externally. The data on RXD pin is sampled on rising edge of the RXC . The
content of the receiver buffer is compared with the first SYNC character at
every edge until it matches. If 8251 is programmed for two SYNC
characters, the subsequent received character is also checked. When the
characters match, the hunting stops.
The SYNDET pin set high and is reset automatically by a status read
operation. In the external SYNC mode, the synchronization is achieved by
applying a high level on the SYNDET input pin that forces 8251 out of HUNT
mode. The high level can be removed after one RXC cycle. The parity and
overrun error both are checked in the same way as in asynchronous mode.
4.2.3. SYNCHROUNS MODE TRASMIT
AND RECEIVE DATA FORMAT
4.3. COMMAND INSTRUCTION
DEFINATION
The command instruction controls the actual operations of the selected
format like enable transmit/receive, error reset and modem control. A
reset operation returns 8251 back to mode instruction format.
4.3.1. CODE INSTRUCTION FORMAT
4.4. STATUS READ DEFINATION
This definition is used by the CPU to read the status of the active 8251
to confirm if any error condition or other conditions like the
requirement of processor service has been detected during the
operation.
4.4.1. STATUS READ INFORMATION
FORMAT
 
5. INTERFACING 8251 WITH 8086
• The chip select for I/O mapped devices are generated by using a 3-to-
8 decoder.
• The address lines A5, A6 and A7 are decoded to generate eight chip
select signals (IOCS-0 to IOCS-7) and in this, the chip select signal
IOCS-2 is used to select 825lA.
• The address line A0 and the control signal M/IO(low) are used as
enable for
• The line A1 of 8086 is connected to C/D(low) of 8251A to provide the
internal addresses.
• The lines D0 – D7 connected to D0 – D7 of the processor to achieve
parallel data transfer.
• The RESET and clock signals are supplied by 8284 clock generator.
Here the processor clock is directly connected to 8251A. This clock
controls the parallel data transfer between the processor and 825lA.
• The peripheral clock (PCLK) supplied by 8284, is divided by suitable
clock dividers like programmable timer 8254 and then used as clock
for serial transmission and reception.
• In 8251A the transmission and reception baud rates can be different
or same.
• The TTL logic levels of the serial data lines and the control signals
necessary for serial transmission and reception are converted to
RS232 logic levels using MAX232 and then terminated on a standard
9-pin D-.type connector.
• The device, which requires serial communication with processor, can
be connected to this 9-pin D-type connector using 9-core cable.
• The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt
signals to initiate interrupt driven data transfer scheme between
processor and 8251 A.
ADDRESSES OF INTERNAL DEVICES OF 8251A
REFERENCES
• Microprocessor | 8251 USART retrieved from GeeksforGeeks,
Wikipedia.
• 8251 Pin Diagram in Microprocessor retrieved from Online Electrical
and Electronics study
• 8251 Block Diagram in Microprocessor retrieved from Online
Electrical and Electronics study
• Interfacing 8251A to 8086 processor retrieved from:
http://mediatoget.blogspot.in/2013/01/interfacing-8251a-to-8086-
processor.html