Verilog HDL 18EC56

Module 2
Basic Concepts,
Modules and Ports
Dinesh M.A.
[email protected]
•
/dinesh.ajay
/prof.dineshma
 VISION OF THE DEPARTMENT

• To be recognized by the society at large as

offering Value based Quality Education to
groom the next generation entrepreneurs,
leaders and researchers in the field of
Electronics and Communication to meet the
challenges at global level.

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 MISSION OF THE DEPARTMENT

• To groom the students with strong foundations of Electronics and

Communication Engineering and to facilitate them to pursue higher
education and research.
• To educate and prepare the students to be competent to face the challenges of
the industry/society and /or to become successful entrepreneurs.
• To provide ethical and value-based education by promoting activities
addressing the societal needs.
• Enable students to develop skills to solve complex technological problems of
current times and also provide a framework for promoting collaborative and
multidisciplinary activities.

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 Program Educational Objectives (PEOs)

• Be able to have a successful career in dynamic industry

that is global, multidisciplinary, and evolving.
• Solve problems, design and innovate while they work
individually or in teams with sense of  professional ethics
and social responsibility.
• Communicate effectively and manage resources skillfully
as members and leaders of the profession

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 Program Specific Outcomes (PSOs)

• An ability to apply the basic concepts of engineering

science into various areas of Electronics Communication
Engineering.
• An ability to solve complex Electronics and
Communication Engineering problems, using state of the
art hardware and software tools, along with analytical
skills to arrive at cost effective and efficient solutions.

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 Course Outcomes
CO’s DESCRIPTION OF THE OUTCOMES

Present the comprehension of the IC Design flow, syntax, lexical

18EC56.1 conventions, data types, system tasks compiler directives and logic
synthesis in Verilog HDL.
Develop Verilog modules for digital circuits using gate level and
18EC56.2 data flow modeling, behavioral modeling using different control
structures and related statements and for system tasks as well.
Analyze the behavior of structural, dataflow and behavior modeling
18EC56.3
procedures written in Verilog.
Design digital functional blocks for a given set of specifications
18EC56.4
using hierarchical modeling concepts in Verilog.

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 RBT
Module – 2 Level
Basic Concepts: Lexical conventions, data
types, system tasks, compiler directives.
Modules and Ports: Module definition, port L1, L2,
L3
declaration, connecting ports, hierarchical
name referencing.

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 Chapter 3
Basic Concepts

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 Learning Objectives

• Understand lexical conventions for operators, comments, whitespace,

numbers, strings, and identifiers.

• Define the logic value set and data types such as nets, registers, vectors,
numbers, simulation time, arrays, parameters, memories, and strings.

• Identify useful system tasks for displaying and monitoring information, and
for stopping and finishing the simulation.

• Learn basic compiler directives to define macros and include files.

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 Lexical Conventions

• The basic lexical conventions used by Verilog HDL are similar to

those in the C programming language.

• Verilog contains a stream of tokens.

• Tokens can be comments, delimiters, numbers, strings,
identifiers, and keywords.

• Verilog HDL is a case-sensitive language. All keywords are in

lowercase
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 Lexical Conventions (Cont.)
• Whitespace • Comments
• Blank space (\b) • Used for readability and
documentation
• Tab (\t)
• Newline (\n) • Just like C:
• // single line comment
• Whitespace is ignored in • /* multi-line
Verilog except comment
• In strings */
• When separating tokens /* Nested comments
/* like this */ may not be acceptable
(depends on Verilog compiler) */
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• Operators
• Operators are of three types: unary, binary, and ternary.
• Unary operators precede the operand.
• Binary operators appear between two operands.
• Ternary operators have two separate operators that separate
three operands.

a = ~ b; // ~ is a unary operator. b is the operand

a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are operands

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Number Specification
• There are two types of number specification in Verilog: sized and unsized.
• Sized numbers
• Sized numbers are represented as <size> '<base format> <number>
• <size> is written only in decimal and specifies the number of bits in the number.
• Legal base formats are decimal ('d or 'D), hexadecimal ('h or 'H), binary ('b or 'B)
and octal ('o or 'O).
• The number is specified as consecutive digits from 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b,
c, d, e, f.
• Only a subset of these digits is legal for a particular base.
• Uppercase letters are legal for number specification.
4'b1111 // This is a 4-bit binary number
12'habc // This is a 12-bit hexadecimal number
16'd255 // This is a 16-bit decimal number.
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• Unsized numbers
• Numbers that are specified without a <base format> specification
are decimal numbers by default.
• Numbers that are written without a <size> specification have a
default number of bits that is simulator- and machine-specific (must
be at least 32).
23456 // This is a 32-bit decimal number by default
'hc3 // This is a 32-bit hexadecimal number
'o21 // This is a 32-bit octal number

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 X or Z values
• Verilog has two symbols for unknown and high impedance values. These
values are very important for modeling real circuits.
• An unknown value is denoted by an x.
• A high impedance value is denoted by z.
12'h13x // This is a 12-bit hex number; 4 least significant bits unknown
6'hx // This is a 6-bit hex number
32'bz // This is a 32-bit high impedance number
• An x or z sets four bits for a number in the hexadecimal base, three bits for a number in
the octal base, and one bit for a number in the binary base.
• If the most significant bit of a number is 0, x, or z, the number is automatically
extended to fill the most significant bits, respectively, with 0, x, or z. This makes it easy
to assign x or z to whole vector.
• If the most significant digit is 1, then it is also zero extended.

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• Negative numbers
• Negative numbers can be specified by putting a minus sign before the
size for a constant number
• Size constants are always positive
• It is illegal to have a minus sign between <base format> and <number>
• An optional signed specifier can be added for signed arithmetic
-6'd3 // 6-bit negative number stored as 2's complement of 3
-6'sd3 // Used for performing signed integer math
4'd-2 // Illegal specification

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• Underscore characters
• An underscore character "_" is allowed anywhere in a number
except the first character.
• Underscore characters are allowed only to improve readability of
numbers and are ignored by Verilog.

• A question mark "?" is the Verilog HDL alternative for z in

the context of numbers.
• The ? is used to enhance readability in the casex and casez
statements, where the high impedance value is a don't care
condition.
• (Note that ? has a different meaning in the context of user-
defined primitives)
12'b1111_0000_1010 // Use of underline characters for readability
4'b10?? // Equivalent of a 4'b10zz

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• Strings
• A string is a sequence of characters that are enclosed by
double quotes.
• The restriction on a string is that it must be contained on
a single line, that is, without a carriage return. It cannot
be on multiple lines.
• Strings are treated as a sequence of one-byte ASCII
values.
"Hello Verilog World" // is a string
"a / b" // is a string
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• Identifiers
• Identifiers are names given to objects so that they can be
referenced in the design.
• Identifiers are made up of alphanumeric characters, the
underscore ( _ ), or the dollar sign ( $ ).
• Identifiers are case sensitive
• Identifiers start with an alphabetic character or an underscore.
They cannot start with a digit or a $ sign (The $ sign as the first
character is reserved for system tasks).
• Ex: name of a module, wire, variable

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• Keywords
• Keywords are special identifiers reserved to define the
language constructs
• Keywords are in lowercase
reg value; // reg is a keyword; value is an identifier
input clk; // input is a keyword, clk is an identifier

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Data Types

• Value Set: Verilog supports four values levels and eight strengths to
model the functionality of real hardware
• In addition to logic values, strength levels are often used to resolve
conflicts between drivers of different strengths in digital circuits.
• If two signals of unequal strengths are driven on a wire, the stronger
signal prevails. For example, if two signals of strength strong1 and
weak0 contend, the result is resolved as a strong1.
• If two signals of equal strengths are driven on a wire, the result is
unknown. If two signals of strength strong1 and strong0 conflict, the
result is an x.
• Strength levels are particularly useful for accurate modeling of signal
contention, MOS devices, dynamic MOS, and other low-level devices.
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Data Types

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• Nets
• Nets represent connections between hardware elements.
• Just as in real circuits, nets have values continuously driven on them by
the outputs of devices that they are connected to.
• Nets are one-bit values by default unless they are declared explicitly as
vectors.
• The default value of a net is z (except the trireg net, which defaults to
x ).

wire a; // Declare net a for the above circuit

wire b,c; // Declare two wires b,c for the above circuit
wire d = 1'b0; // Net d is fixed to logic value 0 at declaration.
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• Registers
• Registers represent data storage elements. Registers retain
value until another value is placed onto them.
• Do not confuse the term registers in Verilog with hardware
registers built from edge-triggered flipflops in real circuits.
• In Verilog, the term register merely means a variable that
can hold a value. Unlike a net, a register does not need a
driver.
• Verilog registers do not need a clock as hardware
registers do. Values of registers can be changed anytime
in a simulation by assigning a new value to the register.
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• Registers
• Register data types are commonly declared by the keyword reg. The default
value for a reg data type is x.
reg reset; // declare a variable reset that can hold its value
initial // this construct will be discussed later
begin
reset = 1'b1; //initialize reset to 1 to reset the digital circuit.
#100 reset = 1'b0; // after 100 time units reset is deasserted.
end

• Registers can also be declared as signed variables. Such registers can be used for
signed arithmetic.
reg signed [63:0] m; // 64 bit signed value
integer i; // 32 bit signed value

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• Vectors
• Nets or reg data types can be declared as vectors (multiple bit
widths). If bit width is not specified, the default is scalar (1-bit).
wire a; // scalar net variable, default
wire [7:0] bus; // 8-bit bus
wire [31:0] busA, busB, busC; // 3 buses of 32-bit width.
reg clock; // scalar register, default
reg [0:40] virtual_addr; // Vector register, virtual address 41 bits wide

• Vectors can be declared at [high# : low#] or [low# : high#], but the

left number in the squared brackets is always the most significant
bit of the vector. In the example shown above, bit 0 is the most
significant bit of vector virtual_addr.

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• Vector Part Select
• For the vector declarations shown above, it is possible to address
bits or parts of vectors.
busA[7] // bit # 7 of vector busA
bus[2:0] // Three least significant bits of vector bus,
// using bus[0:2] is illegal because the significant bit should
// always be on the left of a range specification
virtual_addr[0:1] // Two most significant bits of vector virtual_addr

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• Variable Vector Part Select
• Another ability provided in Verilog HDL is to have variable part selects
of a vector.
• This allows part selects to be put in for loops to select various parts of
the vector.
• There are two special part-select operators:
[<starting_bit>+:width] - part-select increments from starting bit
[<starting_bit>-:width] - part-select decrements from starting bit
• The starting bit of the part select can be varied, but the width has to be
constant.
• The following example shows the use of variable vector part select:

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• Variable Vector Part Select
reg [255:0] data1; //Little endian notation
reg [0:255] data2; //Big endian notation
reg [7:0] byte;
//Using a variable part select, one can choose parts
byte = data1[31-:8]; //starting bit = 31, width =8 => data[31:24]
byte = data1[24+:8]; //starting bit = 24, width =8 => data[31:24]
byte = data2[31-:8]; //starting bit = 31, width =8 => data[24:31]
byte = data2[24+:8]; //starting bit = 24, width =8 => data[24:31]
//The starting bit can also be a variable. The width has
//to be constant. Therefore, one can use the variable part select
//in a loop to select all bytes of the vector.
for (j=0; j<=31; j=j+1)
byte = data1[(j*8)+:8]; //Sequence is [7:0], [15:8]... [255:248]
//Can initialize a part of the vector
data1[(byteNum*8)+:8] = 8'b0; //If byteNum = 1, clear 8 bits [15:8]

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• Integer
• An integer is a general purpose register data type used for
manipulating quantities. Integers are declared by the keyword
integer.
• Although it is possible to use reg as a general-purpose variable, it is
more convenient to declare an integer variable for purposes such as
counting.
• The default width for an integer is the host-machine word size,
which is implementation-specific but is at least 32 bits.
• Registers declared as data type reg store values as unsigned
quantities, whereas integers store values as signed quantities.

integer counter; // general purpose variable used as a counter.

initial counter = -1; // A negative one is stored in the counter
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• Real
• Real number constants and real register data types are declared
with the keyword real.
• They can be specified in decimal notation (e.g., 3.14) or in scientific
notation (e.g., 3e6, which is 3 x 106).
• Real numbers cannot have a range declaration, and their default
value is 0.
• When a real value is assigned to an integer, the real number is
rounded off to the nearest integer.
real delta; // Define a real variable called delta initial
begin
delta = 4e10; // delta is assigned in scientific notation
delta = 2.13; // delta is assigned a value 2.13
end
integer i; // Define an integer i
initial i = delta; // i gets the value 2 (rounded value of 2.13)
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• Time
• Verilog simulation is done with respect to simulation time.
• A special time register data type is used in Verilog to store simulation time. A
time variable is declared with the keyword time.
• The width for time register data types is implementation-specific but is at least
64 bits.
• The system function $time is invoked to get the current simulation time.
time save_sim_time; // Define a time variable save_sim_time
initial
save_sim_time = $time; // Save the current simulation time
• Simulation time is measured in terms of simulation seconds. The unit is denoted
by s, the same as real time.

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• Arrays
• Arrays are allowed in Verilog for reg, integer, time, real, realtime and
vector register data types.
• Multi-dimensional arrays can also be declared with any number of
dimensions.
• Arrays of nets can also be used to connect ports of generated
instances.
• Each element of the array can be used in the same fashion as a
scalar or vector net.
• Arrays are accessed by <array_name>[<subscript>].

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• Arrays
integer count[0:7]; // An array of 8 count variables
reg bool[31:0]; // Array of 32 one-bit boolean register variables
time chk_point[1:100]; // Array of 100 time checkpoint variables
reg [4:0] port_id[0:7]; // Array of 8 port_ids; each port_id is 5 bits wide
integer matrix[4:0][0:255]; // Two dimensional array of integers
reg [63:0] array_4d [15:0][7:0][7:0][255:0]; //Four dimensional array
wire [7:0] w_array2 [5:0]; // Declare an array of 8 bit vector wire
wire w_array1[7:0][5:0]; // Declare an array of single bit wires

• It is important not to confuse arrays with net or register vectors. A

vector is a single element that is n-bits wide. On the other hand,
arrays are multiple elements that are 1-bit or n-bits wide.

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• Examples of assignments to elements of arrays discussed above are shown below:
count[5] = 0; // Reset 5th element of array of count variables
chk_point[100] = 0; // Reset 100th time check point value
port_id[3] = 0; // Reset 3rd element (a 5-bit value) of port_id array.
matrix[1][0] = 33559; // Set value of element indexed by [1][0] to 33559
array_4d[0][0][0][0][15:0] = 0; //Clear bits 15:0 of the register accessed by indices
[0][0][0][0]
port_id = 0; // Illegal syntax - Attempt to write the entire array
matrix [1] = 0; // Illegal syntax - Attempt to write [1][0]..[1][255]

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• Memories
• In digital simulation, one often needs to model register files, RAMs, and
ROMs.
• Memories are modeled in Verilog simply as a one-dimensional array of
registers.
• Each element of the array is known as an element or word and is
addressed by a single array index.
• Each word can be one or more bits.
• It is important to differentiate between n 1-bit registers and one n-bit
register.
• A particular word in memory is obtained by using the address as a
memory array subscript.
reg mem1bit[0:1023]; // Memory mem1bit with 1K 1-bit words
reg [7:0] membyte[0:1023]; // Memory membyte with 1K 8-bit words(bytes)
membyte[511] // Fetches 1 byte word whose address is 511.
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• Parameters
• Verilog allows constants to be defined in a module by the
keyword parameter.
• Parameters cannot be used as variables.
• Parameter values for each module instance can be overridden
individually at compile time.
• This allows the module instances to be customized.
parameter port_id = 5; // Defines a constant port_id
parameter cache_line_width = 256; // Constant defines width of cache line
parameter signed [15:0] WIDTH; // Fixed sign and range for parameter WIDTH

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• Strings
• Strings can be stored in reg.
• The width of the register variables must be large enough to hold the string.
• Each character in the string takes up 8 bits (1 byte).
• If the width of the register is greater than the size of the string, Verilog fills bits to
the left of the string with zeros.
• If the register width is smaller than the string width, Verilog truncates the leftmost
bits of the string.
• It is always safe to declare a string that is slightly wider than necessary.

reg [8*18:1] string_value; // Declare a variable that is 18 bytes wide

initial
string_value = "Hello Verilog World"; // String can be stored in variable

• Special characters serve a special purpose in displaying strings, such as newline,

tabs, and displaying argument values.
• Special characters can be displayed in strings only when they are preceded by
escape characters, as shown

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 System Tasks and Compiler Directives

• System Tasks
• Verilog provides standard system tasks for certain routine
operations.
• All system tasks appear in the form $<keyword>.
• Operations such as displaying on the screen, monitoring values
of nets, stopping, and finishing are done by system tasks.

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 Displaying information

• $display is the main system task

for displaying values of variables or
strings or expressions. This is one
of the most useful tasks in Verilog.
• Usage: $display(p1, p2, p3,....., pn);
• p1, p2, p3,..., pn can be quoted
strings or variables or expressions.
The format of $display is very
similar to printf in C.
• A $display inserts a newline at the
end of the string by default. A
$display without any arguments
produces a newline.

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Example 3-3 $display Task
//Display the string in quotes
$display("Hello Verilog World");
-- Hello Verilog World

//Display value of current simulation time 230

$display($time);
-- 230

//Display value of 41-bit virtual address 1fe0000001c at time 200

reg [0:40] virtual_addr;
$display("At time %d virtual address is %h", $time, virtual_addr);
-- At time 200 virtual address is 1fe0000001c

//Display value of port_id 5 in binary

reg [4:0] port_id;
$display("ID of the port is %b", port_id);
-- ID of the port is 00101
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Example 3-3 $display Task
//Display x characters
//Display value of 4-bit bus 10xx (signal contention) in binary
reg [3:0] bus;
$display("Bus value is %b", bus);
-- Bus value is 10xx

//Display the hierarchical name of instance p1 instantiated under

//the highest-level module called top. No argument is required. This
//is a useful feature)
$display("This string is displayed from %m level of hierarchy");
-- This string is displayed from top.p1 level of hierarchy

//Display special characters, newline and %

$display("This is a \n multiline string with a %% sign");
-- This is a
-- multiline string with a % sign
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Monitoring information
• Verilog provides a mechanism to monitor a signal when its value changes. This facility is provided by
the $monitor task.
• Usage: $monitor(p1,p2,p3,....,pn);
• The parameters p1, p2, ... , pn can be variables, signal names, or quoted strings.
• A format similar to the $display task is used in the $monitor task.
• $monitor continuously monitors the values of the variables or signals specified in the parameter list and
displays all parameters in the list whenever the value of any one variable or signal changes.
• Unlike $display, $monitor needs to be invoked only once.
• Only one monitoring list can be active at a time. If there is more than one $monitor statement in your
simulation, the last $monitor statement will be the active statement. The earlier $monitor statements will be
overridden.

• Two tasks are used to switch monitoring on and off.

• Usage: $monitoron;
$monitoroff;
• The $monitoron tasks enables monitoring, and the $monitoroff task disables monitoring during a simulation.
• Monitoring is turned on by default at the beginning of the simulation and can be controlled during the
simulation with the $monitoron and $monitoroff tasks.

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Example 3-5 Monitor Statement

//Monitor time and value of the signals clock and reset

//Clock toggles every 5 time units and reset goes down at 10 time units
initial
begin
$monitor($time, " Value of signals clock = %b reset = %b", clock, reset);
end

Partial output of the monitor statement:

-- 0 Value of signals clock = 0 reset = 1

-- 5 Value of signals clock = 1 reset = 1
-- 10 Value of signals clock = 0 reset = 0

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Stopping and finishing in a simulation

• The task $stop is provided to stop during a simulation.

• Usage: $stop;
• The $stop task puts the simulation in an interactive mode. The
designer can then debug the design from the interactive mode. The
$stop task is used whenever the designer wants to suspend the
simulation and examine the values of signals in the design.

• The $finish task terminates the simulation.

• Usage: $finish;

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Example 3-6 Stop and Finish Tasks

// Stop at time 100 in the simulation and examine the results

// Finish the simulation at time 1000.
initial // to be explained later. time = 0
begin
clock = 0;
reset = 1;
#100 $stop; // This will suspend the simulation at time = 100
#900 $finish; // This will terminate the simulation at time = 1000
end

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Compiler Directives

• All compiler directives are defined by using the `<keyword> construct.

• `define
• The `define directive is used to define text macros in Verilog.
• The Verilog compiler substitutes the text of the macro wherever it encounters a
`<macro_name>.
• This is similar to the #define construct in C.
• The defined constants or text macros are used in the Verilog code by preceding them
with a ` (back tick).

• `include
• The `include directive allows you to include entire contents of a Verilog source file in
another Verilog file during compilation.
• This works similarly to the #include in the C programming language.
• This directive is typically used to include header files, which typically contain global or
commonly used definitions.

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 Example 3-7 `define Directive

//define a text macro that defines default word size

//Used as 'WORD_SIZE in the code
'define WORD_SIZE 32

//define an alias. A $stop will be substituted wherever 'S appears

'define S $stop;

//define a frequently used text string

'define WORD_REG reg [31:0]
// you can then define a 32-bit register as 'WORD_REG reg32;

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Example 3-8 `include Directive

// Include the file header.v, which contains declarations in the

// main verilog file design.v.
'include header.v
...
...
<Verilog code in file design.v>
...
...

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Summary

• Verilog is similar in syntax to the C programming language . Hardware designers with

previous C programming experience will find Verilog easy to learn.

• Lexical conventions for operators, comments, whitespace, numbers, strings, and

identifiers were discussed.

• Various data types are available in Verilog. There are four logic values, each with
different strength levels. Available data types include nets, registers, vectors, numbers,
simulation time, arrays, memories, parameters, and strings. Data types represent
actual hardware elements very closely.

• functions like displaying, monitoring, suspending, and finishing a simulation.

• Compiler directive `define is used to define text macros, and `include is used to include
other Verilog files.
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 Modules

• Basic building block in

Verilog
• Hierarchical design (top-
down vs. bottom-up)
• Multiple modules in a single
file
• Order of definition not
important
Module Example: SR-Latch
 SR-Latch Example
module SR_latch(Q, Qbar, Sbar, Rbar);
output Q, Qbar;
input Sbar, Rbar;

// Instantiate lower level modules

// Note, how the wires are connected in a cross coupled fashion.
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
endmodule

module Top;
wire q, qbar;
reg set, reset;

// Instantiate lower level modules. In this case, instantiate SR_latch

// Feed inverted set and reset signals to the SR latch
SR_latch l1(q, qbar, ~set, ~reset);

// Behavioral block, initial

initial
begin
$monitor($time, " set = %b, reset= %b, q= %b\n",set,reset,q);
set = 0; reset = 0;
#5 reset = 1;
#5 reset = 0; #5 set = 1;
#5 set = 0; reset = 1; #5 set = 0; reset = 0; #5 set = 1; reset = 0;
end
endmodule
 Ports

• Interface of the module to the environment

• Internals of the module are not visible to the environment
• Internals can be changed as long as the interface (ports) is not
changed
 List of Ports

• Example: 4-bit full-adder inside a top module

module fulladd4(sum, c_out, a, b, c_in); // Module with a list

// of ports
module top; // No list of ports, top-level module
// in simulation
 Port Declaration
• All ports in the list of ports must be declared in the module
• Verilog keyword Type (mode) of port
input Input port
output Output port
inout Bidirectional port
• Example:
module fulladd4(sum, c_out, a, b, c_in);
output [3:0] sum;
output c_out;

input [3:0] a, b;
input c_in;
...
endmodule
 Port Declaration (cont’d)

• Note: all ports are wire by default

• No need to declare it again as wire
• If expected to be reg, the port needs to be declared again (only valid for output ports.)
• Example: the q port in DFF module

module DFF(q, d, clk, reset);

output q;
reg q; // Output port q holds value => reg
input d, clk, reset;
...
endmodule
 Module Instantiation
• Recall the Ripple-carry counter and TFF
module TFF(q, clk, reset);
output q;
input clk, reset;
...
endmodule

module ripple_carry_counter(q, clk, reset);

output [3:0] q;
input clk, reset;
//4 instances of the module TFF are created.
TFF tff0(q[0],clk, reset);
TFF tff1(q[1],q[0], reset);
TFF tff2(q[2],q[1], reset);
TFF tff3(q[3],q[2], reset);
endmodule
 Module Instantiation (cont’d)

• General syntax
<module_name> <instance_name>(port connection list);

• Example:
// assuming module ripple_carry_counter(q, clk, reset);
ripple_carry_counter cntr1(wire_vec1, wire2, wire3);
 Port Connection Rules

• Two parts of a port: internal and external to the module

 Port Connection Rules (cont’d)

• Width matching
• Legal to connect items of different sizes
• A warning may be issued by Verilog simulator
• Unconnected ports
• Allowed in Verilog
• Example:
// module fulladd4(sum, c_out, a, b, c_in);
fulladd4 fa0(SUM, , A, B, C_IN); // output port c_out is unconnected
 Port Connection Rules (cont’d)
• Example of illegal port connection
module Top;
// Declare connection variables
reg [3:0] A, B;
reg C_IN;
reg [3:0] SUM;
wire C_OUT;

// Instantiate fulladd4, call it fa0

fulladd4 fa0(SUM, C_OUT, A, B, C_IN);
// Illegal connection because output port sum is connected to reg

...

endmodule // Top
 Connecting Ports to External Signals

• Two ways for port mapping

• Connecting by ordered list
• More intuitive for beginners
• Mostly used when having few ports
• Connecting by name
• Used when having more ports
• Gives independence from order of ports
• The order of ports in the port list of a module can be changed without changing
the instantiations
 Connecting by Ordered List
module fulladd4(sum, c_out, a, b, c_in);
...
endmodule

module Top;
// Declare connection variables
reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;

// Signals are connected to ports in order (by position)

fulladd4 fa_ordered(SUM, C_OUT, A, B, C_IN);
...
endmodule
 Connecting Ports by Name
module fulladd4(sum, c_out, a, b, c_in);
...
endmodule

module Top;
// Declare connection variables
reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;

// Signals are connected to ports by name

fulladd4 fa_byname(.c_out(C_OUT), .sum(SUM), .b(B), .a(A));
...
endmodule
 Hierarchical Names

• Hierarchical design
• An identifier for every signal, variable, or module instance
• The same identifier can be used in different levels of the hierarchy
• Hierarchical name referencing
• Unique name to every identifier in the hierarchy
• Syntax:
<top-module-name>.<instance-name>.<identifier>
 Hierarchical Names (cont’d)

Stimulus

m1
S
set q
Q

qbar
reset R Qbar
 Hierarchical Names (cont’d)
module stimulus;
Stimulus
wire q, qbar;
reg set, reset;
SR_latch m1(q, qbar, ~set, ~reset);
m1
initial S
...
set q
Q
endmodule
module SR_latch(Q, Qbar, S, R);
output Q, Qbar;
input S, R; qbar
nand n1(Q, S, Qbar); reset R Qbar
nand n2(Qbar, R, Q);
endmodule
• Hierarchical names
stimulus stimulus.q
stimulus.qbar stimulus.set
stimulus.reset stimulus.m1
stimulus.m1.Q stimulus.m1.Qbar
stimulus.m1.S stimulus.m1.R
stimulus.n1 stimulus.n2
 Text

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