ARM Introduction

• The ARM7TDMI processor is a member of the Advanced RISC

machine family of general purpose 32-bit microprocessor

• What does mean ARM7TDMI ?

ARM7 - 32-bit Advanced RISC Machine
T - Thumb architecture extension
• Two separate instruction sets, 32-bit ARM instructions
and 16-bit Thumb instructions
D - Debug extension
M - Enhanced multiplier
I - Embedded ICE macrocell extension
• Von Neumann Architecture
• 3-stage pipeline
– fetch, decode, execute
• 32-bit Data Bus
• 32-bit Address Bus
• 37 32-bit registers
• 32-bit ARM instruction set
• 16-bit THUMB instruction set
• 32x8 Multiplier
• Barrel Shifter
 ARM operating states
• The ARM7TDMI processor has two operating states:
– ARM state which executes 32-bit, word aligned ARM instructions
– THUMB state which can execute 16-bit, halfword aligned THUMB instructions

• Switching state
– Entering THUMB state
• BX instruction with the state bit (bit 0) set in the operand register.
• Automatically on return from an exception (IRQ, FIQ, ABORT, SWI,…), if
the exception was entered with the processor in THUMB state.
– Entering ARM state
• BX instruction with the state bit clear in the operand register.
• Automatically on the processor taking an exception. In this case, the PC is
placed in the exception mode’s link register.
 ARM7TDMI Operating Modes
• The ARM7TDMI supports seven modes of operation:
– User (usr): The normal ARM program execution state
– FIQ (fiq): Designed to support a data transfer or channel process
– IRQ (irq): Used for general-purpose interrupt handling
– Supervisor (svc): Protected mode for the operating system
– Abort mode (abt): Entered after a data or instruction prefetch abort
– System (sys): A privileged user mode for the operating system
– Undefined (und): Entered when an undefined instruction is executed

• Mode changes may be made under software control, or may be brought about by
external interrupts or exception processing.
– Most application programs will execute in User mode. The non-user modes'
known as privileged modes-are entered in order to service interrupts or
exceptions, or to access protected resources.
• The ARM7TDMI has a total of 37 registers:
– 31 general-purpose 32-bit registers
– 6 status registers

• These registers cannot all be seen at once. The

processor state and operating mode dictate
which registers are available to the
programmer.
The THUMB state registers relate to the ARM state registers in the
following way:
 Program Status Registers (1/3)
• The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program
Status Registers (SPSRs) for use by exception handlers.

• These register's functions are:

– Hold information about the most recently performed ALU operation
– Control the enabling and disabling of interrupts
– Set the processor operating mode
Condition Code Flags
The N, Z, C and V bits may be changed as a result of arithmetic
and logical operations, and may be tested to determine whether
an instruction should be executed
In ARM state, all instructions may be executed conditionally.
In THUMB state, only the Branch instruction is capable of
conditional execution.

Control Bits
The I, F, T and M[4:0]) bits will be changed when an exception
arises. If the processor is operating in a privileged mode, they can
also be manipulated by software.
T bit:
This reflects the operating state. When this bit is set, the
processor is executing in THUMB state, otherwise it is
executing in ARM state. This is reflected on the TBIT
external signal.
Note that the software must never change the state of the
TBIT in the CPSR. If this happens, the processor will enter
an unpredictable state.
• Control Bits
– Interrupt disable bits:
• The I and F bits are the interrupt disable bits. When set,
these disable the IRQ and FIQ interrupts respectively.

– Mode bits:
• The M4, M3, M2, M1 and M0 bits (M[4:0]) are the
mode bits. These determine the processor's operating
mode. Not all combinations of the mode bits define a
valid processor mode. Only those explicitly described
shall be used. The user should be aware that if any
illegal value is programmed into the mode bits, M[4:0],
then the processor will enter an unrecoverable state. If
this occurs, reset should be applied.
• Exceptions arise whenever the normal flow of a program has to be halted
temporarily
– For example to service an interrupt from a peripheral.

• ARM supports 7 types of exception and has a privileged processor mode for each
type of exception.

• ARM Exception vectors

Address Exception Mode in Entry

0x00000000 Reset Supervisor
0x00000004 Undefined instruction Undefined
0x00000008 Software Interrupt Supervisor
0x0000000C Abort (prefetch) Abort
0x00000010 Abort (data) Abort
0x00000014 Reserved Reserved
0x00000018 IRQ IRQ
0x0000001C FIQ FIQ
 ARM organization A[31:0] control

address register
• Register file –
P
– 2 read ports, 1 write port + C incrementer

1 read, 1 write port reserved for r15

PC
(pc) register
bank
• Barrel shifter – shift or rotate one operand
instruction
for any number of bits decode
• ALU – performs the arithmetic and logic A
L
multiply &
register
functions required U
A B
control
b
• Memory address register + incrementer u b b
s u u
• Memory data registers s barrel
shifter
s

• Instruction decoder and associated

control logic ALU

data out register data in register

D[31:0]

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 A[31:0] control

address register

P
C incrementer

PC
register
bank

instruction
decode
A multiply &
L register
U control
A B
b
u b b
s u u
s barrel s
shifter

ALU

data out register data in register

D[31:0]
 Three-stage pipeline
• Fetch
– the instruction is fetched from memory and placed in the instruction
pipeline
• Decode
– the instruction is decoded and the datapath control signals prepared
for the next cycle; in this stage the instruction owns the decode logic
but not the datapath
• Execute
– the instruction owns the datapath; the register bank is read, an
operand shifted, the ALU register generated and written back into a
destination register

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ARM single-cycle instruction
pipeline

1 fetch decode execute

2 fetch decode execute

3 fetch decode execute

instruction
time

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 ARM single-cycle instruction
pipeline

fetch decode execute add add r0,r1,#5

sub r2,r3,r6 fetch decode execute sub

cmp r2,#3 fetch decode execute cmp

1 2 3 time

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 ARM multi-cycle instruction
pipeline
Decode logic is always generating
the control signals for the datapath
1 fetch ADD decode execute to use in the next cycle

2 fetch STR decode calc. addr. data xfer

3 fetch ADD decode execute

4 fetch ADD decode execute

5 fetch ADD decode execute

instruction
time

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ARM development tools
 ARM organization
A[31:0] control

address register
• Register file –
P
– 2 read ports, 1 write port + C incrementer

1 read, 1 write port reserved for register

PC

r15 (pc) bank

• Barrel shifter – shift or rotate one instruction

decode
operand for any number of bits A
L
multiply
register
&
U
• ALU – performs the arithmetic and b
A B
control

logic functions required u

s
b
u
s barrel
b
u
s
shifter
• Memory address register +
incrementer ALU
• Memory data registers
• Instruction decoder and associated
control logic data out register data in register

D[31:0]

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 Data processing instruction
datapath activity
 Reg-Reg
address register address register
 Rd = Rn op Rm
 r15 = AR + 4 increment increment
AR = AR + 4 Rd PC Rd PC
registers registers
 Reg-Imm Rn Rm Rn
 Rd = Rn op Imm
mult mult
 r15 = AR + 4
as ins. as ins.
AR = AR + 4
as instruction as instruction
[7:0]

data out data in i. pipe data out data in i. pipe

(a) register – register operations (b) register – immediate operations

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SIR (store register) datapath activity.
 STR (store register) datapath activity
 Compute address
 AR = Rn op Disp address register address register

 r15 = AR + 4 increment increment

 Store data PC Rn PC
registers
 AR = PC Rn
registers
Rd
 mem[AR] =
mult mult
Rd<x:y>
shifter
 If autoindexing lsl #0

=>
= A / A +B/ A -B = A +B/ A -B
Rn = Rn +/- 4
[11:0]

data out data in i. pipe byte? data in i. pipe

(a) 1st cycle – compute address (b) 2nd cycle – store data & auto-index

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The first two (of three) cycles of a branch
instruction.
 The first two (of three) cycles of a branch
instruction
 Compute target
address register address register
address
AR = PC + Disp,lsl #2 increment increment

 Save return address R14

registers registers
(if required) PC PC

r14 = PC mult
mult
AR = AR + 4
lsl #2 shifter

Third cycle: do a small

= A+B =A
correction to the value stored
in the link register in order [23:0]
that it points to directly at the
instruction which follows the data out data in i. pipe data out data in i. pipe
branch?

(a) 1st cycle – compute branch (b) 2nd cycle – save return address
target

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