Design and Verification of RV32I RISC-V

Processor with 2-way Associative Cache

Domain - Computer Architecture, VLSI

Athira V R, Nishanthi G
910019106007, 91001910028
ECE Dept – 8th semester
Anna University Regional Campus, Madurai

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 Overview
1. Objective
7. Hardware and Software
Requirement
2. Introduction
8. Weakly Timeline
3. Existing System
9. First Review
4. Literature Survey
10. Second Review
5. Problem Identification
11. Result and Conclusion
6. Proposed System 12. Reference

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 Objective

• To implement the design specification of RISC-V processor by

HDL.
• Then UVM framework for individual components are
developed and verified.
• Finally the design is implemented in Altera Cyclone II FPGA.

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 Introduction

RISC-V

• Origin of RISC-V : In 2010, at Berkeley University Computer

Architecture group, Kryste Asanovic started as a 3 month summer project.
• Principle Designers : Andrew Waterman, Yunsup Lee, David Patterson,
Kryste Asanovic.
• Why RISC-V? Simplicity, Open Source, New Business Model, On par
with modern CPU.
• RISC-V Base ISA : RV32E, RV32I, RV64I, RV128I.
Std. Extension : M, A, F, D,Q

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RV32I

• RISC-V 32-bit Integer ISA.

• Registers : x0 – x32
• 32-bit wide (1 word)
• 32-bit Address Space.

RISC-V IP Core
• 5 stage pipeline stage – IF, ID, EXE, MEM, WB.
• 2-way associative instruction cache.
• 2-way associative data cache with write-back and allocate on wire.
• 2xAXI4 master port for CPU access to instruction/data/pheripheral.

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 Existing System
1. The existing design of RV32I is based on non-pipelined, Van
Neuman architecture along with direct-mapped cache.
2. The existing verification mostly used is formal verification.

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 Literature Survey
S.NoAuthor Name Year Paper Title Description Advantages Disadvantages
1 Aaron
. Elson 2022 Five-Stage * This paper implemented five- * Forwarding Unit * Not
Phangestu,Dr. Ir. Pipelined 32- stage pipelined soft processor Optimized
Totok Mujiono, Bit RISC-V core. the clock
M.I.Kom, Ahmad Base Integer * The core uses the RISC-V signal,
Zaini ST Instruction Set RV32I Base Integer Instruction lead to
Architecture Set Architecture. wastage of
Soft * The CPU core executed all cycles
Microprocesso the RV32I instructions, except
r FENCE, ECALL, and CSR
Core in VHDL instructions.
* The proposed processor core
runs on 2115 LUTs, 558 flip-
flops, and 67,608memory bits,
with a maximum frequency of
62.95 MHz.

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2 Roberto Molina-Robles,
Literature Survey
2022 A compact * The structure of a functional verification flow * Two hierarchical * Grey Box
Edgar Solera-Bolanos, functional used for the design of a RISC-V core is levels- Block-level, Approach
Ronny Garc´ıa-Ram´ırez, verification flow presented. Chip-level
.
Alfonso Chac´on-Rodr´ıguez, for a RISC-V 32I * The paper offers a guide on the test-planning * Regression Test
Alfredo Arnaudy based core used and details of the flow architecture, showing Module
and Renato Rimolo-Donadio how to integrate the Universal Verification * The designed flow is
Methodology with the required, reference compact yet efficient,
models, while implementing key futures in making it affordable.
standard verification environments, such as
testing regressions and code and structural
coverage.

3 Adrian Oleksiak, 2020 Design and * This paper design and verified RISC-V * Diassembler *Emulator
Sebastian Cieslak, Verification processor core.
Krzysztof Marcinek, Environment * The environment module consists of Emulator
Witold A. Pleskacz for RISC-V and Disassembler.
Processor Cores * The Emulator is coupled with the RTL
processor model’s executed instructions flow.
* In case of any inconsistency, emulator reports a
particular error.
* Disassembler module shows instruction
executed by the running core in human
understandable ASCI format.

4 Abdelrahman Adel, 2021 Implementation  * This paper proposes a solution, which  * The verification  * The UVM
Dina Saad, and Functional integrates a environment is environment
Mahmoud Abd El Mawgoed, Verification of hardware security intellectual property (IP), a modular, reusable, and was not able to
Mohamed Sharshar, RISC-V Core for UART IP for scalable testbench test the whole
Zyad Ahmed, Secure IoT communication with the external world, and a frameworks that are SoCs 
Hala Ibrahim, Applications core based on the RISCV ISA. used to validate
Hassan Mostafa * The full system implements a system-on-chip to numerous designs
act as an end node for IoT systems usually named Design
Under Test

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 Literature Survey
5 Aslesa Singh 2022 Design and * In this paper, a 32-bit Datapath with RISC * Optimization of * Increased
Neil Franklin Implementation instruction set architecture based on RV32I CPU Utilization report and Latency

.
Nidhi Gaur of a 32-bit ISA instruction Memory report * Reduced
RISC-V set has been designed. * Using Pre-Decode Throughput
Processor Core * Furthermore, through analysis of function and stage * Reduced
using Virtex-7 theory of RISC-V CPU instruction set, the * Branch Prediction Speed
and Virtex- processor has been optimized by designing a six unit
UltraScale staged folded pipeline core.
* The design has been examined on the current
industrial standards FPGA boards.
* Synthesis and implementation on two Boards of
Virtex family has been
compared on the basis of Utilization reports and
Power
Reports.

6 Luca Zulberti 2021 A Script-Based This paper presented a verification framework to * The solution is * Complex in
Pietro Nannipieri and Luca Cycle-True speed up versatile and nature
Fanucci Verification the hardware/software co-design of SoC extensible. * Requires
Framework solutions focussing on * Flexibility in license
to Speed-Up cycle-true analyzes exploiting RISC-V integrating the design
Hardware and architecture. with other tools
Software Co-
Design of
System-on-Chip
exploiting RISC-
V Architecture

7 Hossameldin Eassa 2019 RISC-V based * This paper presents a RISC-V based A comparison of Utilization of
Ihab Adly implementation architecture execution time, Intel FPGA
Hanady H. Issa of Programmable for implementing Programmable Logic Controller approximated total Cyclone V is
Logic Controller (PLC) on thermal power low
on FPGA for Field Programmable Gate Array (FPGA). dissipation, Digital
Industry 4.0 * It consists of two internal timers, two UART Signal Processor
Peripherals, ROM, RAM, Core. (DSP),
and FPGA resources
consumption is done.

8 NGUYEN MY QUI , CHANG 2022 Design and * This study proposes a general-purpose 256-bit * Use of dynamic Lack of compilers
HONG LIN , AND POKI Implementation VLIW instruction scheduler &
CHEN of a 256-Bit architecture based on the new RISC-V instruction RISC-V GNUtoolchain
RISC-V-Based set architecture * 6 Pipeline Stage
Dynamically
Scheduled
Very Long
Instruction Word
on FPGA

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 Literature Survey
.
9 J. Vitor Rafael Chrisóstomo, 2018 “Entendendo a * Maestro is a five-stage RV32I ISA pipeline * It was created * Problem in
necessidade de implementation based on David Patterson and primarily for the flushing
uma isa John Hennessy’s Computer Organization and educational purposes unit due to
aberta e Design RISC-V Edition. about RISC-V, the timing error.
implementação * The project is entirely academic; it was ISA, and processor * Timing
de um núcleo developed at the Federal University of Rio design. problem with
risc-v,” Grande do Norte in Brazil, and the creator didn’t the overall
intend to compete with complex implementations. processor core,
and it was not
able to be run
in an actual
FPGA.

10 M. B. Petersen 2021 Ripes: A visual This paper implemented single-cycle RV32I soft * Able to run most of * Due to the
computer processor the instruction unoptimized
architecture nature of
simulator singlecycle
processors, it
runs on a
slightly longer
clock period.

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 Problem Identification

• Unnecessary wastage of clock cycle.

• Reduced throughput.
• Increased power consumption.
• Increased miss rate.
• Occurrence of pipeline hazards.

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 Proposed System

The proposed system uses 5-stage pipelined architecture along

with 2-way associative cache for Data and Instruction. It also
solves the problem of control hazards by placing hazard unit.

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 Hardware and Software Requirement

Hardware
• Xilinx Spartan 6 FPGA

Software
• QuestaSim-64 10.6c
• Xilinx
• GVIM Text editior
• Linux Ubuntu 20.04

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 Weakly Timeline

Week 1-2 • General specification

• Signal Definition.

Week 3-4 • Specify components

• Architecture

Week 5-7 • Design Testcases

• Design

Week 8-12 • Block level verification

• Chip level Verification.

Week 13-15 • Implementation on FPGA.

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 Design Specifications

• ISA – Fixed 32-bit encoding, 16-bit immediate

• Processor – 32 bit.
• Linear and Synchronous pipeline.
• Pipeline stage – 5 (IF, ID, EXE, MEM, WB)
• Little endian memory system.
• Type of core instruction format : R, I, S, B, L
• 28 Instruction
• Clock Speed – 500 MHz
• 5 cycle structural latency
• Memory is organized as 256 * 32
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 Instruction Type Instruction
R - TYPE ADD
  SUB
  SLL
  SLT
  XOR
  SRL
  OR
  AND
I - TYPE ADDI
  XORI
  ORI
  ANDI
S - TYPE SW
  SB
B - TYPE BEQ
  BNE
  BLT
  BGE
  BLTU
  BGEU
L - TYPE LB
  LW

Fig 1.1 : RISC-V Base Integer Register state Fig 1.2 : Instructions

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 Design Partition

• Top Down Approach

Fig 1.3 – Design Partition

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 Architecture

Fig 1.3 – 5-stage pipeline design architecture of RV32I

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 Architecture Components

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 Design Entry & Signal Specifications
MAIN MODULE clk1
clk2
IF IF_ID_IR
IF_ID_PC
IF_ID_NPC
ID ID_EX_A
ID_EX_B
ID_EX_IMM
ID_EX_IR
ID_EX_NPC
EXE EX_MEM_IR
EX_MEM_B
EX_MEM_ALUOUT Design Entry
EX_MEM_COND
MEM MEM_WB_IR • Schematics Entry
MEM_WB_ALUOUT
MEM_WB_LMD • HDL
WB ID_EX_TYPE • FSM
EX_MEM_TYPE • EDIF
MEM_WB_TYPE

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 Schematics Result

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 Schematics Result

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 Result & Conclusion

• By using Functional Verification, perform and verify all the

testcases.
• Achieve 100% Functional Coverage.
• Observe the result in XILINX SPARTAN 6 FPGA Board.

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 Reference

[1] Roberto Molina-Robles, Edgar Solera-Bolanos, Ronny Garc´ıa-Ram´ırez, Alfonso

Chac´on-Rodr´ıguez, Alfredo Arnaudy and Renato Rimolo-Donadio, “A compact
functional verification flow for a RISC-V 32I based core”, 2020.
[2]Aslesa Singh, Neil Franklin, Nidhi Gaur, Paursuh Bhulania, “Design and
Implementation of a 32-bit ISA RISC-V Processor Core using Virtex-7 and Virtex-
UltraScale”,2020.
[3] NGUYEN MY QUI , CHANG HONG LIN , (Member, IEEE), AND POKI CHEN, “Design
and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction
Word on FPGA”,2020.
[4] Adrain Oleksiak, Sebastian Cieslak, Krzysztof Marcinek, Wintold A Pleskacz,“Design and
Verification Environment for RISC-V Processor Cores”,2019.
[5] Aaron Elson Phangestu, Dr. Ir. Totok Mujiono, Ahmad Zaini ST,“Five-Stage Pipelined 32-Bit
RISC-V Base Integer Instruction Set Architecture Soft Microprocessor Core in VHDL”,2021

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 Reference
[6] Aaron Elson Phangestu,Dr. Ir. Totok Mujiono, M.I.Kom, Ahmad Zaini ST , “Five-Stage
Pipelined 32-Bit RISC-V Base Integer Instruction Set Architecture Soft Microprocessor Core in
VHDL”, 2021.
[7] Roberto Molina-Robles, Edgar Solera-Bolanos, Ronny Garc´ıa-Ram´ırez, Alfonso Chac´on-
Rodr´ıguez, Alfredo Arnaudy and Renato Rimolo-Donadio, “A compact functional verification
flow for a RISC-V 32I based core”, 2022.
[8] Adrian Oleksiak, Sebastian Cieslak, Krzysztof Marcinek, Witold A. Pleskacz, “Design and
Verification Environment for RISC-V Processor Cores”, 2022.
[9] Abdelrahman Adel, Dina Saad, Mahmoud Abd El Mawgoed, Mohamed Sharshar, Zyad
Ahmed, Hala Ibrahim, Hassan Mostafa, “Implementation and Functional Verification of RISC-V
Core for Secure IoT Applications”,2021
[10] Aslesa Singh, Neil Franklin, Nidhi Gaur, “Design and Implementation of a 32-bit ISA RISCV
Processor Core using Virtex-7 and Virtex-UltraScale”, 2022.

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