UNIT- 1:
Basics of Microcontroller
& Intel 8051 architecture
Dr. Pawar Bhalchandra B.
Architecture of 8051
The 8051 Architecture - specific features
The 8 bit CPU with Registers A (Accumulator) and B
Sixteen bit Program Counter (PC) and Data Pointer (DPTR)
8-bit Program Status word (PSW) and Stack Pointer (SP)
Internal ROM or EPROM (8751) of 0 (8031) to 4K (8051)
Internal RAM of 128 bytes
Four Register banks, each containing eight registers
Sixteen bytes, which may be addressed at the bit level
Eighty bytes of general purpose data memory
Thirty-two I/O pins arranged as Four 8-bit ports: P0-P3
Two 16-bit Timers / Counter: T0 and T1
Full duplex serial data receiver/transmitter : SBUF
Control registers: TCON, TMOD, SCON, PCON, IP and IE
Two external and Three internal interrupt sources
Oscillator and clock circuits
A and B CPU Register
The 8051 contains 34 general purpose or working registers.
Two of these Register A and B.
The immediate result is stored in the accumulator
register (Acc) for next operation.
The B register is a register just for multiplication and
division operation which requires more register spaces
for the product of multiplication and the quotient and
the remainder for the division.
Program status word(PSW)
The program status word shown in figure.
The PSW contain the math flags, User program flag
F0,and the register select bits that identify which of the
four General-purpose register banks is currently in
use by the program.
The math flags include carry(c),auxiliary carry(AC),
overflow(OV) and parity(p)
Program Status Word (PSW)
Program counter (PC)
The program counter points to the address of the next
instruction to be Executed
As the CPU fetches the opcode from the program ROM, the
program counter is increasing to point to the next instruction.
The program counter is 16 bits wide
This means that it can access program addresses 0000
to FFFFH, a total of 64K bytes of code
Data pointer (DPTR)
The data pointer is 16 bit register.
It is used to hold the address of the data in the memory.
The DPTR register can be accessed separately as lower
eight bit(DPL) and higher eight bit (DPH).
It can be used as a 16 bit data register or two
independent data register.
Stack and Stack Pointer (SP)
The stack is a section of RAM used by the CPU to store
information temporarily
This information could be data or an address
‰The register used to access the stack is called the SP
(stack pointer) register
The stack pointer in the 8051 is only 8 bit wide.
The 8051 oscillator and clock
The 8051 requires an external oscillator circuit. The oscillator circuit
usually runs around 12MHz. The crystal generates 12M pulses in
one second.
A machine cycle is minimum amount time must take by simplest
machine instruction
An 8051 machine cycle consists of 12 crystal pulses (clock cycle).
The first 6 crystal pulses (clock cycle) is used to fetch the Opcode
and the second 6 pulses are used to perform the operation on the
operands in the ALU.
This gives an effective machine cycle rate at 1MIPS (Million
Instructions Per Second).
Oscillator circuit and timing
Internal memory
128 bytes of RAM.
Directly addressable range: 00
to 7F hexadecimal.
Indirectly addressable range: 00
to FF hexadecimal.
Bit addressable space:
20 to 2F hexadecimal .
Four register banks:
00 to 1F hexadecimal.
Internal RAM
The 128 byte internal RAM shown in above
figure It is organized into three areas.
1.Working register:
Thirty-two bytes from address 00h to 1Fh that make up 32 working
register organized as Four bank of eight bit each.
Bits RS0 and RS1 in the PSW determine which bank of register is
currently Is use.
Bank 0 is selected upon reset
2.Bit addressable:
A bit addressable area of 16 bytes occupies RAM bytes addresses
20h to 2Fh,forming A total of 128 addressable bits.
An addressable bit may be specified by its bit address of 00h to
7Fh.
3.General purpose:
A general-purpose RAM area above the bit area,form 30h to
7Fh,addresable as bytes.
Internal RAM Organization
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External memory
External memory is used in cases when the internal ROM and
RAM memory Available On chip is not sufficient.
Two separate memories are made available by the 16-bit PC and
the DPTR and by different control pins for enabling external
ROM and RAM chips.
If the 128 bytes of internal RAM is insufficient, the external
RAM is accessed by the DPTR.
In the 8051 family, external RAM of upto 64 KB can be added to
any chip.
Special Function Register (SFR)
The SFR (Special Function Register) can be
accessed by their names or by their addresses.
The SFR registers have addresses between
80H and FFH.
Not all the address space of 80 to FF is
used by SFR.
The unused locations 80H to FFH are
reserved and must not be used by the 8051
programmer.
There are 21 SFRs.
Special Function Register Map
Addresss↓↓Bit Addressable
F8
F0 B
E8
E0 ACC
D8
D0 PSW
C8
C0
B8 IP
B0 P3
A8 IE
A0 P2
98 SCON SBUF
90 P1 TMOD TL0 TL1 TH0 TH1 PCON
88 TCON SP DPL DPH
80 P0
80 81 82 83 84 85 86 87
Special Function Register (SFR)cont..
Special Function Register (SFR)cont..
128 byte address space,
directly addressable as 80 to FF
hex.
16 addresses are bit
addressable: (those ending in 0
or 8).
This space contains:
Special purpose CPU registers.
I/O ports.
Interrupt control
Timers
Special Function Register (SFR)cont..
CPU registers:
- ACC : Accumulator.
-B : B register.
- PSW : Program
Status Word.
- SP : Stack Pointer.
- DPTR : Data Pointer
Interrupt control: (DPH, DPL).
-IE : Interrupt Enable.
-IP : Interrupt Priority.
I/O Ports:
- P0 : Port 0.
- P1 : Port 1.
- P2 : Port 2.
- P3 : Port 3.
Special Function Register (SFR)cont..
Timers:
- TMOD : Timer mode.
- TCON : Timer control.
- TH0 : Timer 0 high byte.
- TL0 : Timer 0 low byte.
- TH1 : Timer 1 high byte.
- TL1 : Timer 1 low byte.
Serial I/O:
- SCON : Serial port control.
- SBUF : Serial data registers.
Other:
- PCON : Power control
Summary – SFR’s
Register Bit Primary Function Bit Addressable Register
A 8 Math, data manipulation Y A
B 8 Math Y B
PC 16 Addressing program bytes N PC
DPTR 16 Addressing code and external data N DPTR
SP 8 Addressing internal RAM stack data N SP
PSW 8 Processor status Y PSW
P0-P3 8 Store I/O port data Y P0-P3
TH0/TL0 8/8 Timer/counter 0 N TH0/TL0
TH1/TL1 8/8 Timer/counter 1 N TH1/TL1
TCON 8 Timer/counter control Y TCON
TMOD 8 Timer/counter control N TMOD
SBUF 8 Serial port data N SBUF
SCON 8 Serial port control Y SCON
PCON 8 Serial port control. user flags N PCON
IE 8 Interrupt enable control Y IE
IP 8 Interrupt priority control Y IP
8051 Microcontroller - PIN Diagram
I/O Ports
-Four 8-bit I/O ports.
Port 0
Port 1
Port 2
Port 3
- Most have alternate functions.
- Quasi-bidirectional:
Port
0
- Port 0 is a dual purpose port, it is located from pin 32 to pin 39
(8 pins).
- To use this port as both input/output ports each pin must be connected
externally to pull-up resistor.
- As an I/O port.
- Alternate functions:
As a multiplexed data bus.
8-bit instruction bus, strobed by PSEN.
Low byte of address bus, strobed by
ALE. 8-bit data bus, strobed by WR and
RD.
Port
1
- Port 1 is a dedicated I/O port from pin 1 to pin 8.
- Upon reset it is configured as outport.
- It is generally used for interfacing to external device
- thus if you need to connect to switches or LEDs, you could make use of
these 8 pins,
- but it doesn’t need any pull- up resistors as it is having internally
- As an I/O port: Standard quasi-bidirectional.
Port
2
- Like port 0, port 2 is a dual-purpose port.(Pins 21 through 28)
-It can be used for general I/O or as the high byte of the address bus for
designs with external code memory.
- Like P1 ,Port2 also doesn’t require any pull-up resistors
- As an I/O port:
Standard quasi-bidirectional.
- Alternate functions:
High byte of address bus for externalprogram and data
memory accesses.
Port
3
- Port 3 is also dual purpose but designers generally avoid using this
port unnecessarily for I/O because the pins have alternate functions
which are related to special features of the 8051.
- Indiscriminate use of these pins may interfere with the normal
operation of the 8051.
- As an I/O port:
Standard quasi-bidirectional.
- Alternate functions:
Serial I/O -
TXD, RXD Timer clocks
- T0, T1 Interrupts -
I/O Port structure
The internal circuitry for the I/O port is shown in
the figure
If you want to read in from a pin, you must first give
a logic ‘1’ to the port latch to turn off the FET
otherwise the data read in will always be logic ‘0’.
When you write to the port you are actually writing
to the latch e.g. a logic 0 given to the latch will be
inverted and turn on the FET which cause the port
pin to be connected to Gnd (logic 0).
I/O Port structure Diagram
Sachin Bhalavat (9409049436)
The 8051’s derivatives
