AVR Architecture and Application
AVR Architecture and Application
S u m a i y a Ta s n i m
Lecturer(Provisional)
Department of CSE
Va r e n d r a U n i v e r s i t y
CSE-425
Reference: Third chapter of textbook
Acknowledgment: Some websites and Shayban Nasif Tonmoy Sir
Sections
Program Timer/
SRAM EEPROM USART TWI ADC
ROM Counter
CPU
MCU
OSC Control Watchdog Interrupt
I/O Ports SPI ISP
& Timing Timer Unit
Crystal
Oscillator
Internal PORTA PORTB PORTC PORTD
Oscillator
1. CPU
CPU is like a brain of the controller which helps in executing a number of
instructions. It can handle interrupts, perform calculations and control
peripherals with the help of registers. ATmega series comes with two
buses called instruction bus and data bus.
The CPU reads the instructions in the instruction bus while data bus is
used to read or write the corresponding data. The CPU mainly consists of
the program counter, general purpose registers, stack pointer, instruction
register and an instruction decoder.
2. ROM
The controller program is stored in ROM, also known as non-volatile
programmable flash memory. The flash memory comes with a resolution of at
least 10,000 write/erase cycles. Flash memory is mainly divided into two parts
known as Application flash section and booth flash section.
Program of the controller is stored in the applications flash section. While
booth flash section is optimized to work directly when the controller is
powered up.
3. RAM
The SRAM (static random access memory) is used for storing information
temporarily and comes with 8-bit registers. This is just like a regular
computer RAM which is used to supply data through the runtime.
4. EEPROM
The EEPROM (Electronically Erasable Programmable Read Only Memory) is
non-volatile memory used as a long time storage. It has no involvement in
executing the main program. It is used for storing the configuration of the
system and device parameters which continues to work in the reset of the
application processor.
EEPROM comes with a limited write cycle up to 100,000 while read cycles
are unlimited. While using EEPROM, write minimum instructions as per
requirement, so you can get benefit from this memory for a longer time.
5. Interrupt
The interrupt is used for an emergency which puts the main function on
hold and executes the necessary instructions at that time. Once the
interrupt is called and executed the code switches back to the main
program.
6. Analog and Digital I/O Modules
Digital I/O modules are used to set a digital communication between the
controller and external devices. While analog I/O modules are used for
transferring analog information. Analog comparators and ADC fall under
the category of analog I/O modules.
7. Timer/Counter
Timers are used for calculating the internal signal within the controller. Atmega16
comes with two 8-bit timers and one 16-bit timer. All these timers work as a counter
when they are optimized for external signals.
8. Watchdog Timer
The watchdog timer is a remarkable addition in this controller which is used to
generate the interrupt and reset the timer. It comes with 128kHz distinct CLK
source.
9. Serial Communication
Atmega16 comes with USART and SPI units that are used for developing serial
communication with the external devices.
H a r v a r d A r c h i t e c t u r e i n t h e AV R :
Program General
Flash ROM
CPU Purpose RAM EEPROM Timers
Registers
Feature-1:
RISC(Reduced Instruction Set Computer) processors have a fixed instruction size.
In a CISC microcontroller such as 8051, instructions can be 1,2 or even 3 bytes.
This variable instruction size makes the task of the instruction decoder very
difficult because the size of the incoming instruction is never known.
In a RISC architecture, the size of all instructions is fixed. Therefore, the CPU can
decode the instructions quickly. Like a bricklayer working with bricks of the same
size as opposed to using bricks of variable sizes. Of course, using bricks of the
same sizes is much more efficient.
AVR uses mostly 2-byte instructions with very few 4-byte instructions.
Feature-2:
A major characteristic of RISC architecture is a large number of registers.
Because of which, the need for a large stack to store parameters can be avoided.
Although a stack can be implemented on a RISC processor, it is not essential as in
CISC because so many registers are available. All RISC architectures have at least
32 registers. Among those, only a few are assigned to a dedicated function.
In AVR, there are 32 general purpose registers and they are the same as
accumulator in other microprocessors. Thus they can be used by all arithmetic and
logic instructions. They are R0-R31 and all of them are of 8 bits.
Feature-3:
RISC processors have a small instruction set, which makes the job of assembly
language programmers much more tedious and difficult compared to CISC
assembly language programming. This is one reason that RISC is used more
commonly in high-level language environments such as the C programming
language rather than Assembly language environments.
It is noticeable that CISC is sometimes called as ‘Complete instruction set
computer’ instead of ‘Complex instruction set computer’ because it has a
complete set of every kind of instruction. But how many of these instructions are
used and how often is another matter to be considered.
The limited number of instructions in RISC leads to programs that are large.
Although these programs can use more memory, this is not a problem as memory
is considerably cheap. In the AVR we have around 130 instructions.
Feature-4:
The most important characteristic of RISC processor is that more than 95% of
instructions are executed with one clock cycle, in contrast to CISC instructions.
Even some of the 5% of the RISC instructions that are executed with two clock
cycles can be executed with one clock cycle by juggling instructions around (code
scheduling). Code scheduling is most often the job of the compiler.
Feature-5:
RISC processors have separate buses for data and code. In all the x86 processors,
like all other CISC computers, there is one set of buses for the address and
another set of buses for data.
In RISC processors, there are four sets of buses: 1) a set of data buses for carrying
data(operands) in and out of the CPU, 2) a set of address buses for accessing the
data, 3) a set of data buses to carry the opcodes , and 4) a set of address buses to
access the opcodes.
The use of separate buses for code and data operands is commonly referred to as
Harvard Architecture.
Feature-6:
Because of a large number of instructions, moreover, each with so many different
addressing modes, microinstructions(microcode) are used to implement them in
CISC processors. The implementation of microinstructions inside the CPU
employs more than 40-60% of transistors in many CISC processors.
RISC instructions are implemented using the hardwire method which takes no
more than 10% of the transistors.
Feature-7:
RISC uses load/store architecture.
In CISC microprocessors, data can be manipulated while it is still in memory. For example,
in instructions such as “ADD Reg, Memory”, the microprocessor must bring the contents of
the external memory location into the CPU to add it to the contents of the registers. The
problem is there might be a delay in accessing the data from external memory. Then the
whole process would be stalled, preventing other instructions from proceeding in the
pipeline.
In RISC, instructions can only load from external memory into registers or store registers
into memory locations. There is no direct way of doing arithmetic and logic operations
between a register and the contents of external memory locations. All these instructions
must be performed by first bringing both operands into the registers inside the CPU, then
performing the arithmetic or logic operation, and then sending the result back to memory.
This idea is commonly known as load/store architecture.
ATmega32 Block Diagram
VCC PA0-PA7 PC0-PC7
GND
PORTA DIGITAL INTERFACE PORTC DIGITAL INTERFACE
AVCC
MUX & ADC ADC INTERFACE
TWI
AREF STACK POINTER
PROGRAM COUNTER
TIMERS/COUNTERS OSCILLATOR
SRAM
PROGRAM FLASH INTERNAL
GENERAL PUPOSE
OSCILLATOR
REGISTERS XTAL1
INSTRUCTION X
REGISTER Y WATCHDOG TIMER
Z OSCILLATOR
CONTROL LINES
INTERNAL
AVR CPU STATUS REGISTER
INTERRUPT UNIT
CALIBRATED RESET
OSCILLATOR
PROGRAMMING
EEPROM
LOGIC SPI
+
- COMP INTERFACE USART
PB0-PB7 PD0-PD7
Classification of microcontroller
Microcontroller
16 bit ECL
32 bit
Microcontrollers are broadly classified into four types based on:
• TTL is commonly used, CMOS consumes low power. ECL is fast processor
• Width of data format: It means the size of the operand upon which processor can
operate. Based on this we have 4-bit, 8-bit, 16-bit, and 32-bit microcontrollers.
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