TON DUC THANG UNIVERSITY
FACULTY OF ELECTRICAL & ELECTRONICS ENGINEERING
DEPARTMENT OF ELECTRONICS & TELECOMMUNICATIONS ENGINEERING
CHAPTER 6:
FUNCTIONS OF
COMBINATIONAL LOGIC
DIGITAL SYSTEM DESIGN 1
402061
ACKNOWLEDGEMENT
The picture content of this slide is from
Thomas L. Floyd, [2015],Digital Fundamentals,
11e. Prentice Hall.
402061 - CHAP 6: FUNCTIONS OF
3/24/2016 2
COMBINATIONAL LOGIC
OUTLINE
1. Half and Full Adders
2. Parallel Binary Adders
3. Ripple Carry and Look-Ahead Carry Adders
4. Comparators
5. Encoders/Decoders
6. Code converters
7. Multiplexers/Demultiplexers
8. Parity Generators/Checkers
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OBJECTIVES
Distinguish between half and full adders
Implement multibit parallel binary adders,
ripple carry and look-ahead carry parallel
adders
Describe comparator
Implement a basic binary decoder, use BCD-
to-7-segment decoder to display systems…
Use MUX/DEMUX
Explaining the meaning of parity, the use of
checkers
3/24/2016 402061 - CHAP 6: FUNCTIONS OF COMBINATIONAL LOGIC 4
HALF ADDER
Inputs Outputs
A B Cout S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
S S
A S
B Cout A
Cout
B
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FULL ADDER
Inputs Outputs
S
A B Cin Cout S A S
0 0 0 0 0 B
0 0 1 0 1 Cout
0 1 0 0 1 Cin
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 S S
A A S A S Sum
B B Cout B Cout
Cin
Cout
3/24/2016 402061 - CHAP 6: FUNCTIONS OF COMBINATIONAL LOGIC 6
PARALLEL ADDER
A4 B 4 A3 B3 A2 B2 A1 B1
C0
A B Cin A B Cin A B Cin A B Cin
Cout S Cout S Cout S Cout S
C4
C3 C2 C1
S4 S3 S2 S1
The output carry (C4) is not ready until it
propagates through all of the full adders.
ripple carry, delaying the addition process.
3/24/2016 402061 - CHAP 6: FUNCTIONS OF COMBINATIONAL LOGIC 7
PARALLEL ADDER
S
1 1
Binary 2 2 4-bit
number A 3 3 sum
4 4
1
Binary 2
number B 3
4
Input Output
C0 C4
carry carry
74LS283 features look-ahead carry, which adds
logic to minimize the output carry delay.
maximum delay to the output carry is 17 ns
3/24/2016 402061 - CHAP 6: FUNCTIONS OF COMBINATIONAL LOGIC 8
COMPARATOR
COMP
A0 0
A1 A
A2
A3 3
Cascading A>B A>B
A=B A=B Outputs
inputs
A<B A<B
B0 0
B1 A
B2
B3 3
74LS85
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COMPARATOR
Comparing two 4-bit number for equality
A1
B1
A2
B2 Output
A3
B3
A4
B4
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COMPARATOR
IC comparators can be expanded using the
cascading inputs.
The lowest order comparator has a HIGH on the
A = B input. LSBs MSBs
A0 COMP A4 COMP
A1 0 A5 0
A2 A A6 A
A3 A7
3 3
A>B A>B A>B A>B
+5.0 V A=B A=B A=B A=B Outputs
A<B A<B A<B A<B
B0 0 B4 0
B1 A B5 A
B2 B6
B3 3 B7 3
3/24/2016 402061 - CHAP 6: FUNCTIONS OF COMBINATIONAL LOGIC 11
ENCODER
BCD-to-Binary encoder:
1
A0
2
3
A1
4
5 A2
6
7
8
A3
9
3/24/2016 402061 - CHAP 6: FUNCTIONS OF COMBINATIONAL LOGIC 12
ENCODER
Decimal-to-BCD encoder:
VCC
1 0 1 (16)
A0 (11) HPRI/BCD
2 0 1
1 (12)
2
3 1 (13)
A1 3
1
(9)
(1)
4 (7)
4 0 Decimal (2) 2 BCD
0 0 5 (6)
5 0 A2 input (3) 4 output
6 0 6 (14)
(4) 8
7 7
8 0 0 (5) 8
A3 (10)
9
0
9
(8)
74HC147
GND
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DECODER
Binary-to-decimal decoder:
Bin/Dec
0 1
1 1
2 1
3 1
4 1
1 A0 5 1
6 1
4-bit binary 1 A1 7 1 Decimal
input 0 A2 8 1 outputs
9 1
1 A3 10 1
11 0
12 1
13 1
14 1
15 1
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DECODER
74HC154: a 4-to-16 decoder X/Y
0
1
2
3
4
5
A0 1 6
A1 2 7
A2 4 8
A3 8 9
10
11
12
13
14
CS1 & 15
CS2 EN
74HC154
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DECODER
74HC42: BCD-to-decimal decoder
BCD/DEC (1)
0
(2)
1
(3)
2
(15) (4)
A0 1 3
(14) (5)
A1 2 4
(13) (6)
A2 4 5
(12) (7)
A3 8 6
(9)
7
(10)
8
(11)
9
74HC42
3/24/2016 402061 - CHAP 6: FUNCTIONS OF COMBINATIONAL LOGIC 16
DECODER
74LS47: a BCD-to-seven segment display with
active LOW outputs V
CC
(16)
BCD/7-
seg BI/RBO (4)
BI/RBO
(13)
(7) a
1 (12)
(1) b
BCD 2 (11)
(2) c Output
inputs 4 (10) s to
(6) d
8 (9) seven
e
(3) (15) segme
LT LT f nt
(5) (14)
RBI RBI g device
(8)
74LS47
GND
3/24/2016 402061 - CHAP 6: FUNCTIONS OF COMBINATIONAL LOGIC 17
DECODER
74LS47 features leading zero suppression
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0
RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1
74LS47 74LS47 74LS47 74LS47
g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO
Blanked Blanked
3/24/2016 402061 - CHAP 6: FUNCTIONS OF COMBINATIONAL LOGIC 18
CODE CONVERTER
To convert different types of code
LSB
LSB
MSB MSB
Binary-to-Gray Gray-to-Binary
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Multiplexer
Multiplexer (MUX) selects data from many
input lines
MUX
0
S0 0
Data 1 1
select S1
D0 0 Data
D1 1 output
Data
D 2
inputs D2
3 3
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Demultiplexer
Demultiplexer (DEMUX) switches data from
one input line to many output lines
DEMUX
Y0
Data A0
Y1
select A1
lines Y2
A2 Data
Y3
outputs
Y4
Enable G1
Y5
G2A
inputs Y6
G2B
Y7
74LS138
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PARITY GENERATOR
Reading assignment:
DIGITAL FUNDAMENTALS 11th edition (borrow
from the library)
Section 6-10 pg 358
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SUMMARY
In this chapter, we have learned:
different types of adder
the description of comparator
the implementation of a basic binary
decoder, use BCD-to-7-segment decoder to
display systems…
MUX/DEMUX
the meaning of parity and the use of
checkers
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HW #6
DIGITAL FUNDAMENTALS 11th edition (borrow
from the library)
Summary the applied logic: traffic signal
controller (pg 365)
Prob: pg 373 – 381 every even problem
Prepare chap 7: Latches, flip-flops and
timers
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