Chapter Eight

Counters

Prepared by: Tesfaye B

Target Group: ECE 3rd Year Students
Adapted from Esubalew M. and Addisalem H., DBU

.
Debre Berhan University, February 2013 E.C.
 Topics
• Introduction to counters
• Asynchronous counters
• Synchronous counters
• Up/down counters
• Design of synchronous counters
 Digital Counters
Introduction
• a counter is a sequential logic circuit consisting of a set of
flip flops which can go through a sequence of states.

Figure 1. State diagram of three bit binary counter

• Counter circuits are the best example for the flip flop
applications.
Debre Berhan University, February 2013 E.C.
 Digital Counters…

• Common tasks of counter

 Count up or down
 Increment or decrement count
 Sequence events
 Divide frequency
• Counters can be classified as:
 Asynchronous/ripple counter and
 Synchronous counter

Debre Berhan University, February 2013 E.C.

 Digital Counters…
• Asynchronous Counters (or Ripple counters)
The clock signal (CLK) is only used to clock the first FF.
Each FF (except the first FF) is clocked by the preceding FF.
• Synchronous Counters,
The clock signal (CLK) is applied to all FF, which means that
all FF shares the same clock signal,
Thus the output will change at the same time.

Debre Berhan University, February 2013 E.C.

 Digital Counters…

• Modulus (MOD) – the number of states it counts in a

complete cycle before it goes back to the initial state.
• Thus, the number of flip-flops used depends on the MOD of
the counter (ie; MOD-4 use 2 FF (2-bit), MOD-8 use 3 FF
(3-bit), etc..).
• Maximum count
– 4 bit = 24 = 0000 to 1111 in binary
– 8 bit = 28 = 0000 0000 to 1111 1111 in binary

Debre Berhan University, February 2013 E.C.

 Asynchronous counter

• The Asynchronous Counter that counts 4 number starts from

00 01 10 11 and back to 00 is called MOD-4 Ripple
(Asynchronous) Up-Counter
• State table and state diagram
Present State Next State

Q1Q0 Q1Q0
00 01
01 10
10 11
11 00
State table State diagram
Debre Berhan University, February 2013 E.C.
 Asynchronous counter…
• MOD 4 Asynchronous Up Counter
 A two-bit asynchronous counter is shown
on the left. The external clock is connected
to the clock input of the first flip-flop (FF0)
only. So, FF0 changes state at the falling
edge of each clock pulse, but FF1 changes
only when triggered by the falling edge of
the Q output of FF0.

 Note that for simplicity, the transitions of

Q0, Q1 and CLK in the timing diagram
above are shown as simultaneous even
though this is an asynchronous counter.
Actually, there is some small delay between
the CLK, Q0 and Q1 transitions.

Debre Berhan University, February 2013 E.C.

 Asynchronous counter…
Why it is called ripple counter? Observe the timing diagram of
Asynchronous counter.

Debre Berhan University, February 2013 E.C.

 Asynchronous counter…
• MOD 8 Asynchronous Up Counter
 The following is a three-bit asynchronous
binary counter and its timing diagram for
one cycle. It works exactly the same way as
a two- bit asynchronous binary counter
mentioned above, except it has eight states
due to the third flip-flop.

Present State Next State

CBA CBA
000 001
001 010
010 011
011 100
100 101
101 110
110 111
111 000
Debre Berhan University, February 2013 E.C.
 Asynchronous counter…
• MOD 16 Asynchronous Up Counter

Debre Berhan University, February 2013 E.C.

 Asynchronous Counters (MOD ≠ 2N)

• So far, we have design the counters with MOD number equal to

2N, where N is the number of bit (N = 1,2,3,4….) (also
correspond to number of FF)
• Thus, the counters are limited on for counting MOD-2, MOD-4,
MOD-8, MOD-16 etc..
• The question is how to design a MOD-5, MOD-6, MOD-7,
MOD-9 which is not equal to MOD 2N (MOD2≠N) ?
• MOD-6 counters will count from 010 (0002) to 510(1012) and after
that will recount back to 010 (0002) continuously

Debre Berhan University, February 2013 E.C.

 Asynchronous Counters (MOD ≠ 2N)

• MOD-6 ripple up-counter (MOD ≠ 2N

Present St. Next St.
CBA CBA
000 001
001 010
010 011
011 100 Figure: State Diagram
100 101
101 000(110)
Reset the state to 0002
Figure :Next State Table when 1102 is detected

Debre Berhan University, February 2013 E.C.

 Asynchronous Counters (MOD ≠ 2N)

• MOD-6 ripple up-counter (MOD ≠ 2N

Detect the output at

CBA=110 to activate
CLR. NAND gate is
used
to detect outputs that
generates ‘1’! Debre Berhan University, February 2013 E.C.
Asynchronous Counters (MOD ≠ 2N)…

Exercise 1:
1. Draw MOD-5 and MOD-10 (Decade) Ripple Up- counter (MOD ≠
2 N)

Debre Berhan University, February 2013 E.C.

 Synchronous Counters

• A Synchronous in contrast to an Asynchronous is one whose output

bits change state simultaneously, with no ripple. The only way we can
build such a counter circuit from J-K flip-flops is to connect all the
clock inputs together, so that each and every flip-flop receives the exact
same clock pulse at the exact same time:

Debre Berhan University, February 2013 E.C.

 Synchronous Counters…

• A 4 bit Synchronous up counter:

Debre Berhan University, February 2013 E.C.

 Design of Synchronous Counters

Procedure to design synchronous counter are as follows:-

Step 1: Obtain the State Diagram.
Step 2: Obtain the Excitation Table using state transition table for any
particular FF (JK or D or T). Determine number of FF used.
Step 3: Obtain and simplify the function of each FF input using K-Map.
Step 4: Draw the circuit.

Debre Berhan University, February 2013 E.C.

 Synchronous Counters Design…

Example: Design a MOD-4 synchronous up-counter, using

JK FF.
Step 1: Obtain the State Diagram.

0 00

Binary 11 01
3 1

2 10
 Synchronous Counters Design…

Step 2: Obtain the Excitation Table, two J K flip flops are used.
Present State Next State Input, J K
B A B A J B KB JA KA

0 0 0 1 0 1 X

X
0 1 1 0 1 X 1

X OUTPUT TRANSITION FF INPUT

1 0 1 1 X 1 X QN QN+1
0 J K
1 1 0 0 X X 1 0 0 0 X
1 0 1 1 X
1 0 X 1
1 1 X 0
Step 3: Obtain the simplified function using K-Map.

A A 0 1

B 0 1
B
0 0 1
JB = A
0
X X KB = A
1
X X 1 0 1

A A 0 1
0 1 B
B
0
X 1 KA = 1
0 1 X JA = 1
1 1 X 1
1 X
•Step 4: Draw the circuit
A (LSB) B (MSB)

1
JA QA J B QB
CLK CLK

KA Q A KB QB

(MOD-4 synchronous up-counter )

Exercise 2:
1. Design a 3 bit synchronous up /down counter using J-K
and T flip flop
How To Design Synchronous Counter that count Random
number?
Example: design a Synchronous Counter to Count 4,7,3,0 and
2 respectively using JK Flip Flop negative triggered by
showing:
i. Flip Flop Used
ii. State Transition Diagram
iii. Exitation Table / Present state, next State
iv. Karnough Map & perform Simplified Function
v. The Synchronous Counter
Synchronous Counter to Count 4,7,3,0 and 2 respectively
Solution:
Step 1 : Flip Flop Used
Find Modulo, N= 2n

M = 7, M = 2n-1 = 7

n
2 =N , so, N = 7+1 = 8, MOD 8

2n = 8, n = 3

n = 3 bit = 3 Flip Flop.

Synchronous Counter to Count 4,7,3,0 and 2 respectively
Step 2 : State Transation Exitation Truth Table For Counter
Diagram, to count 4, 7, 3, 0 using JK FlipFlop
and 2. Present Next J K
Qn State
100 Qn+1
0 0 0 x
010
111
0 1 1 x

1 0 x 1
000 011 1 1 x 0
Synchronous Counter to Count 4,7,3,0 and 2 respectively

Step 3 : Exitation Table /present State, Next State

Deci Present Next State JC KC JB KB JA KA
mal State
QC QB QA QC QB QA

4 1 0 0 1 1 1 x 0 1 x 1 x
7 1 1 1 0 1 1 x 1 x 0 x 0
3 0 1 1 0 0 0 0 x x 1 x 1
0 0 0 0 0 1 0 0 x 1 x 0 x
2 0 1 0 1 0 0 1 x x 1 0 x
Synchronous Counter to Count 4,7,3,0 and 2 respectively
Step 4: Karnough Map and
Simplified Function

CB 00 01 11
10
A
0 K-Map For
0 0 x 1 JA = QC
1
x x x x
Synchronous Counter to Count 4,7,3,0 and 2 respectively
Step 5 : Perform Counter Circuit
KA = QC,
By using simplified function from K-Map, JA = QC,
JB = 1, KB = QC, JC = QA + QB, KC = QB
Exercise 3:
1. Design a counter to count in the following sequence:
15,9,11,5,2,13,1.
Thank you,
Questions?

Debre Berhan University, February 2013 E.C.