Chapter 8

Shift Registers

Dr Abdelaziz Yousif
Ahmed 22-03-23
Ext: 7845

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 Course Outcome
1. Explain number systems, codes, digital arithmetic operation and
circuits.
2. Use Boolean algebra and Karnaugh Maps to minimize Boolean
expressions for the design of digital logic circuits.
3. Explain and use flip-flops, latches, counters, multiplexers
and de-multiplexers.
4. Design and construct combinational digital logic circuits using
appropriate logic design techniques.
5. Design and construct synchronous sequential digital
logic circuits using appropriate logic design techniques.

Digital Fundamentals, Eleventh Edition, Global Edition Copyright © 2016 by Pearson Education, Ltd.
Thomas L. Floyd All Rights Reserved
 Learning Outcome

1. Identify the basic forms of data movement in shift registers

2. Explain how serial in/serial out, serial in/parallel out, parallel in/serial
out, and parallel in/parallel out shift registers operate
3. Describe how a bidirectional shift register operates
4. Determine the sequence of a Johnson counter
5. Set up a ring counter to produce a specified sequence
6. Construct a ring counter from a shift register
7. Use a shift register as a time-delay device
8. Use a shift register to implement a serial-to-parallel data converter

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 Outline

1. Shift Register Operations

2. Types of Shift Register Data I/Os
3. Bidirectional Shift Registers
4. Shift Register Counters
5. Shift Register Applications

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 Shift register Operations
Basic Shift Register Operations
A shift register is group of flip-flops is used to store more
that 1-bit.
Some basic data movements are illustrated here.
Data in

Data in Data out Data out Data in Data out

Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out

Data in

Data in

Data out Data out

Serial in/parallel out Parallel in/parallel out Rotate right Rotate left

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 Type of Shift Register Data I/O
Serial-in/Serial out Shift Register
Shift registers are available in IC form or can be constructed
from discrete flip-flops as is shown here with a five-bit serial-in
serial-out register.
Each clock pulse will move an input bit to the next flip-flop. For
example, a 1 is shown as it moves across.

FF0 FF1 FF2 FF3 FF4

Serial 1 1 1 1 1 1 Serial
data data
D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4
input output
C C C C C

CCL
L KK

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 Type of Shift Register Data I/O
Serial-in/Serial out Shift Register
The serial in/serial out shift register accepts data serially that is,
one bit at a time on a single line. It produces the stored
information on its output also in serial form.

1010

Initial 0 0 0 0
1 0 0 0 0
2 1 0 0 0
3 0 1 0
0
4 1 0 1
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 Type of Shift Register Data I/O
Serial-in/Serial out Shift Register

Initial 1 0 1 0
5 0 1 0 1
6 0 0 1 0
7 0 0 0 1
8 0 0 0 0

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 Type of Shift Register Data I/O
Serial-in/Serial out Shift Register - Example
Show the states of the 5-bit register in figure below for the
specified data input and clock waveforms. Assume that the
register is initially cleared (all 0s).

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 Type of Shift Register Data I/O
Serial-in/Serial out Shift Register

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 Type of Shift Register Data I/O
Serial-in/Parallel out Shift Register
 Data bits are entered serially (least-significant bit first) into a serial
in/parallel out shift register in the same manner as in serial in/serial out
registers.
 The difference is the way in which the data bits are taken out of the
register; in the parallel output register, the output of each stage is
available.
 Once the data are stored, each bit appears on its respective output line,
and all bits are available simultaneously, rather than on a bit-by-bit basis
as with the serial output.

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 Type of Shift Register Data I/O
Serial-in/Parallel out Shift Register - Example
Show the states of the 4-bit register (SRG 4) for the data input
and clock waveforms in Figure below. The register initially
contains all 1s.

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 Type of Shift Register Data I/O
Serial-in/Parallel out Shift Register - Example

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 Type of Shift Register Data I/O
Parallel in/Serial out Shift Register
Shift registers can be used to convert parallel data to
serial form. A logic diagram for this type of register is
shown:
D0 D1 D2
D3

SHIFT/LOAD
G1 G5 G6 G3 G7
G2 G4

Serial
D D D D
Q0 Q1 Q2 Q3 data out
C C C C

FF0 FF1 FF2 FF3

CLK

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 Type of Shift Register Data I/O
Parallel in/Serial out Shift Register
D2 D3
D0 D1
SHIFT/LOAD

G1 G5 G2 G6 G3 G7 G4

Q0 Q1 Q2 Q3

FF0 FF1 FF2

CLK FF3

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 Type of Shift Register Data I/O
Parallel in/Serial out Shift Register
Load mode

D0 D1 D2 D3
0 1 1
SHIFT/LOAD 1 1
0 0 0 0

G1 G5 G2 G6 G3 G7 G4

0 D1 0 D2 0 D3
D0
0 0 0 0 Serial
D1
Q 1 D2
D D D D
Q0 Q2 D3
Q3 data out
C C C C

FF0 FF1 FF2 FF3

CLK

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 Type of Shift Register Data I/O
Parallel in/Serial out Shift Register
Shift mode

D0 D1 D2 D3
1 0 0
SHIFT/LOAD 0 0
1 1 1
1

G1 G5 G6 G7
G2 G4
0
G3
Q0 0 Q2 0
Q1
Q0 Serial
Q 1 Q1
D D D D
Q0 Q2 Q2
Q3 data out
C C C C

FF0 FF1 FF2 FF3

CLK

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 Type of Shift Register Data I/O
Parallel In/Parallel Out Shift Registers
The parallel in/parallel out register employs both methods.
Immediately following the simultaneous entry of all data bits, the bits
appear on the parallel outputs.

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 Bidirectional Shift Register
A bidirectional shift register is one in which the data can be shifted
either left or right.
A HIGH on the RIGHT/LEFT control input allows data bits inside the
register to be shifted to the right, and a LOW enables data bits inside the
register to be shifted to the left.
When the RIGHT/LEFT control input is HIGH, gates G1 through G4 are
enabled.
When a clock pulse occurs, the data bit are shifted one place to the right.
When the RIGHT/LEFT control input is LOW, gates G5 through G8 are
enabled.
When a clock pulse occurs, the data bits are then shifted one place to the
left.

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 Bidirectional Shift Register

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 Bidirectional Shift Register
RIGHT/LEFT

Serial
data in

G1 G5 G2 G6 G3 G7 G4 G8

FF0 FF1 FF2

CLK FF3

Q0 Q1 Q2 Q3

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 Bidirectional Shift Register
Bidirectional Shift Register (shift right)
0 0 0 0
1 1 1 1
1 Din
Din Din
Din
Din

0 0 0 0
Din Din Din Din

Din Din Din Din Din

Din Din Din

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 Bidirectional Shift Register
Bidirectional Shift Register (shift left)
1 1 1 1
0 0 0 0
0 Din
Din Din Din
Din

0 0 0 0
Din Din Din Din

Din Din Din Din Din Din

Din Din

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 Bidirectional Shift Register
EXAMPLE
Determine the state of the shift register of Bidirectional Shift
Register after each clock pulse for the given RIGHT/LEFT control
input waveform in (a). Assume that Q0 = 1, Q1 = 1, Q2 = 0, and Q3 = 1
and that the serial data-input line is LOW.

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 Shift Register Counters
The Johnson Counter
 The complement of the output of the last flip-flop is connected
back to the D input of the first flip-flop.
 Johnson counter will produce a modulus of 2n, where n is the
number of stages in the counter.
FF0 FF1 FF2 FF3

The Johnson counter can D0 Q0 D1 Q1 D2 Q2 D3 Q3

be made with a series of D C C C C

flip-flops Q3 Q3

CLK

… or with a series of J-K FF0 FF1 FF2 FF3

Q3

flip flops. Here Q3 and 3 J0 Q0 J1 Q1 J2 Q2 J3 Q3

Q fed back to the J and K

are C C C C
Q3
inputs with a “twist”. K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

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 Shift Register Counters
Johnson Counter
Redrawing the same Johnson counter (without the clock shown)
illustrates why it is sometimes called as a “twisted-ring” counter.
FF0

J0 Q0

“twist” C

K0 Q0

Q3
Q3
Q3

Q
3

Q1

K1

Q1
J1
FF3

FF1
C
C

K3
J3

Q2 K2

Q2 2 J

2FF

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 Shift Register Counters
Five-bit Johnson Counter

1 0

0 0 0 0 0 0
1 1 0 0 0 0
2 1 1 0 0 0
3 1 1 1 0 0
4 1 1 1 1 0
5 1 1 1 1 1
6 0 1 1 1 1
7 0 0 1 1 1
8 0 0 0 1 1
9 0 0 0 0 1

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 Shift Register Counters
Johnson Counter

Timing sequence for a 5-bit Johnson counter

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 Shift Register Counters
Ring Counter
 The only change is the output of the last FF is connected to the input of
first FF0.
 The ring counter can be implemented with either D flip-flops or J-K
flip-flops.

Here is a 4-bit ring

counter constructed from
a series of D flip-flops.
Notice the feedback.

Like the Johnson counter,

it can also be implemented
with J-K flip flops.

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 Shift Register Counters
A 10-bit Ring
Counter

0 1 0 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0 0 0
2 0 0 1 0 0 0 0 0 0 0
3 0 0 0 1 0 0 0 0 0 0
4 0 0 0 0 1 0 0 0 0 0
5 0 0 0 0 0 1 0 0 0 0
6 0 0 0 0 0 0 1 0 0 0
7 0 0 0 0 0 0 0 1 0 0
8 0 0 0 0 0 0 0 0 1 0
9 0 0 0 0 0 0 0 0 0 1
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 Shift Register Counters
Ring Counter -Example
If a 10-bit ring counter similar to the figure below has the initial state
1010000000, determine the waveform for each of the Q outputs.

A 10-bit ring counter

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 Shift Register Counters

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 Shift Register Application
Time Delay
 A serial in/serial out shift register can be used to provide a time delay
from input to output that is a function of both the number of stages (n) in
the register and the clock frequency.
 When a data pulse is applied to the serial input, it enters the first stage on
the triggering edge of the clock pulse. It is then shifted from stage to
stage on each successive clock pulse until it appears on the serial output
n clock periods later.

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 Shift Register Application
Time Delay -EXAMPLE
Determine the amount of time delay between the serial input and
each output. Show a timing diagram to illustrate.

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 Shift Register Application
The clock period is 2 µs. Thus, the time delay can be increased or
decreased in 2 µs increments from a minimum of 2 µs to a maximum of
16 µs.

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 Shift Register
Application
An 8-bit serial in/serial out shift register has a 40 MHz clock. What
is the total delay through the register?
A SRG 8 Q7
Data in Data out
B

The delay for each CLK 40

MHz
C
Q7

clock is 1/40 MHz = 25

25 ns
ns
The total delay is CLK
8 x 25 ns = 200
Data
ns in
Data out
t d = 200 ns

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 Shift Register Application
Serial-to-Parallel Data Converter
 Serial data transmission from one digital system to another
commonly
is used to reduce the number of wires in the transmission line.
 A simplified serial-to-parallel data converter, in which two types of
shift registers are used.

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 Shift Register Application

A UART (Universal Asynchronous Data bus

Receiver Transmitter) is a serial-to-parallel
converter and a parallel to serial converter. Buffer
s

UARTs are commonly used in small Transmitter Receiver

data register data register
systems where one device must
communicate with another. Parallel data
is converted to asynchronous serial form CLK Transmitter
shift register
CLK Receiver
shift register
and transmitted. The serial data format
is: Serial data out Serial data in

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 Shift Register Application
Keyboard Encoder

 The keyboard encoder is an example of where a ring

counter is used in a small system to encode a key press.
 Two 74HC195 shift registers are connected as an 8-bit
ring counter preloaded with a single 0. As the 0 circulate
in the ring counter, it “scans” the keyboard looking for
any row that has a key closure. When one is found, a
corresponding column line is connected to that row line.
The combination of the unique column and row lines
identifies the key. The schematic is shown on the
following slide…

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 Power on LOAD
SH / LD +VCC
Ring counter

D0 D1 D2 D3 D4 D5 D6 D7
J J
K K
CLK
SRG 4 SRG 4 +V
(5 kHz) 74HC195 74HC195
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
C C

Clock inhibit

123456 7 8 1 234567 8
ROW encoder COLUMN encoder
74HC147 74HC147
124 12 4

Switch closure
Q Q
D0 D1 D2 D3 D4 D5
C
Key code register
C C 74HC174
Q0 Q1 Q2 Q3 Q4 Q5

Q
One-shots To ROM

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 Quiz

1. The shift register that would be used to delay serial data

by4 clock periods is Data in

a. c.
Data in Data out Data out

Data in

b. Data in
d.

Data out Data out

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 Quiz
2. The circuit shown is a
a. serial-in/serial-out shift register
b. serial-in/parallel-out shift register
c. parallel-in/serial-out shift register
d. parallel-in/parallel-out shift register
D0 D3

SHIFT / LOAD D1

D2

G4 G1 G5 G2 G6 G3

Serial
D0 Q0 D1 Q1 D2 Q2 D3 Q3 data
out

C C C C

CLK

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 Quiz

3. If the SHIFT/LOAD line is HIGH, data

a. is loaded from D0, D1, D2 and D3 immediately
b. is loaded from D0, D1, D2 and D3 on the next CLK
c. shifted from left to right on the next CLK
d. shifted from right to left on the next CLK
D0 D1 D2
D3

SHIFT /LOAD

G4 G1 G5 G2 G6 G3

Serial
D0 Q0 D1 Q1 D2 Q2 D3 Q3 data
out

C C C C

CLK

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 Quiz

4. A 4-bit parallel-in/parallel-out shift register will store

data for
a. 1 clock period
b. 2 clock periods
c. 3 clock periods
d. 4 clock periods

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 Quiz
5.The 74HC164 (shown) has two serial inputs. If data is
placed on the A input, the B input
a. could serve as an active LOW enable
b. could serve as an active HIGH enable
c. should be connected to ground
d. should be left open
(9)
CLR
(8)
CLK
Serial A (1)
R R R R R R R R

inputs B (2) C C C C C C C C

S S S S S S S S

(3) (4) (5) (6) (10) (11) (12) (13)

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

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 Quiz

6. An advantage of a ring counter over a Johnson counter

is that the ring counter
a. has more possible states for a given number of flip-
flops
b. is cleared after each cycle
c. allows only one bit to change at a time
d. is self-decoding

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 Quiz

7. A possible sequence for a 4-bit ring counter is

a. … 1111, 1110, 1101 …
b. … 0000, 0001, 0010 …
c. … 0001, 0011, 0111 …
d. … 1000, 0100, 0010 …

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 Quiz

8. The circuit shown is a

a. serial-in/parallel-out shift register
b. serial-in/serial-out shift register
c. ring counter
d. Johnson counter
FF0 FF1 FF2 FF3
Q3
J0 Q0 J1 Q1 J2 Q2 J3 Q3

C
C C C
Q3
K0 Q0
K1 Q1 K2 Q2 K3 Q3

CLK

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 Quiz

9. Assume serial data is applied to the 8-bit shift register

shown. The clock frequency is 20 MHz. The first data bit
will show up at the output in
a. 50 ns
b. 200 ns
c. 400 ns
d. 800 ns

A SRG Q7
Data in Data
B 8
out
CL Q7
C
20K
MHz

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 Quiz

10. For transmission, data from a UART is sent in

a. asynchronous serial form
b. synchronous parallel form
c. can be either of the above
d. none of the above

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 Quiz

Answers:

1. a 6. d

2. c 7. d

3. c 8. d

4. a 9. c

5. b 10.
a
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