Digital Logic Design Chapter 5
Digital Logic Design Chapter 5
Example 9:The main stairway in a block of flats has three switches for controlling the
lights. Switch A is located at the top of the stairs, switch B is located halfway up the
stairs and switch C is positioned at the bottom of the stairs. Design a logic network
to control the lights on the staircase.
Example 10: Design a circuit to enable a chemical additive to be introduced into the fluid
through another inlet only when the temperature is not too cold or too hot and the fluid is
above the high- level sensor.
• The two graphic symbols for the NOR gate are shown in Fig. below.
• Example: implement the following Boolean function using only NOR gates.
a. F = (AB + E)(C + D)
b. F = A + (B’ + C)(D’ + BE’)
c. F = (CD + E)(A + B’)
d. F = [(C + D)B' + A](B + C')
e. F = (AB' + CD')E + BC(A + B)
f. F = w(x + y + z) + xy;
Convert the logic diagram the following to a multiple-level NAND and NOR circuit
a) HALF-ADDER
The half-adder accepts two binary digits on its inputs and produces two binary
digits on its outputs, a sum bit and a carry bit.
The Sout represents the least significant bit of the sum.
The Cout represents the most significant bit of the sum.
The Boolean functions for the two output from the truth table:
S = x’y+ xy’ = x⊕y
C = xy
Implementation of Half-Adder
The full-adder accepts two input bits and an input carry and generates a sum
output and an output carry.
The basic difference between a full-adder
and a half-adder is that the full-adder accepts an input carry.
The Boolean functions for the two out put from the truth table:
Using x-OR, S = x’y’z + x’yz’ + xy’z’ + xyz = x⊕y⊕z
C = x’yz + xy’z + xyz’ + xyz = xy + z(x ⊕y)
Implementation of Full Adder with Two Half
Adders and an OR Gate
d) Full-Subtractor
A full-subtractor is a combinational circuit that performs a subtraction between
two bits, taking into account that a 1 may have been borrowed by a lower
significant stage.
This circuit has three inputs and two outputs.
Exercise:- design the full-subtractor combinational logic ckt.
A binary parallel adder is a digital circuit that produces the arithmetic sum of two
binary numbers in parallel.
It consists of full-adders connected in a chain, with the output carry from each full-
adder connected to the input carry of the next full-adder in the chain.
Figure below shows the interconnection of four full-adder (FA) circuits to provide a
4-bit binary parallel adder.
An n-bit parallel adder requires n full-adders.
Example:
a) What are the sum outputs when 111 and 101 are added by the 3-bit parallel adder?
b) What are the sum outputs when 1110 and 1011 are added by the 4-bit parallel adder?
A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines.
If the n-bit decoded information has unused or don't-care combinations, the decoder output
will have fewer than 2n output.
The decoders presented here are called n-to-m-line decoders, where m <= 2 n.
Their purpose is to generate the 2n (or fewer) minterms of n input variables.
The name decoder is also used in conjunction with some code converters such as a BCD-to-
seven segment decoder.
Only one output can be active (high) at any times.
a) Truth table
b) Block diagram
Arbaminch university, AMiT 18
Dept. of Electrical and comp Eng.
Combinational Logic Implementation using decoder
A decoder provides the 2n minterm of n input variables. Since any Boolean function can be
expressed in sum of minterms canonical form, one can use a decoder to generate the
minterms and an external OR gate to form the sum.
In this way, any combinational circuit with n inputs and m outputs can be implemented with
an n-to-2n- line decoder and m OR gates.
The procedure for implementing a combinational circuit by means of a decoder and OR gates
requires that the Boolean functions for the circuit be expressed in sum of minterms.
Example:-Implement a full-adder circuit with a decoder and two OR gates.
From the truth table of the full-adder, we obtain the functions for this combinational circuit
in sum of minterms:
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
Normally every commercially available decoder ICs have a special input other than normal
working input variables called ENABLE.
The use of this ENABLE input is that when activated the complete IC comes to the working
condition for its normal functioning.
If ENABLE input is deactivated the IC goes to sleep mode, the normal functioning is
suspended, and all the outputs become logic 0 irrespective of normal input variables
conditions.
Its function is build higher decoder from lower decoders.
E A B D0 D1 D2 D 3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1 Figure: 2-to-4 decoder with enable input E.
Example:- Construct a 3-to-8 line decoder with the use of a 2-to-4 line decoder.
Example:- Construct a 4-to-16 line decoder with the use of a 2-to-4 line decoder.
Example:- Construct a 5-to-32 line decoder with the use of a 3-to-8 line decoder.
As in decoders, multiplexer ICs may have an enable input to control the operation of the
unit.
When the enable input is in a given binary state, the outputs are disabled, and when it is in
the other state (the enable state), the circuit functions as a normal multiplexer.
The enable input (sometimes called strobe) can be used to expand two or more multiplexer
ICs to a digital multiplexer with a larger number of inputs.
Example:- Construct a 8-to-1 multiplexer with the use of a 4-to-1 line multiplexer and
external gate.
Example:- Construct a 16-to-1 multiplexer
with the use of only a 4-to-1 line multiplexer.
A demultiplexer is a circuit that receives information from a single line and directs it to one
of 2n possible output lines.
The selection of a specific output is controlled by the bit combination of n elected lines.
The term “demultiplex” means one into many.
Whenever information is transmitted from one device (the transmitter) to another device
(the receiver), there is a possibility that errors can occur such that the receiver does not
receive the identical information that was sent by the transmitter.
One of the simplest and most widely used schemes for error detection is the parity method.
Parity Bit:- A parity bit is an extra bit that is attached to a code group that is being
transferred from one location to another.
The parity bit is made either 0 or 1, depending on the number of is that are contained in the
code group. Two different methods are used.
The even-parity method, and
The odd-parity method.
In the even-parity method, the value of the parity bit is chosen so that the total number of
1s in the code group (including the parity bit) is an even number.
In the odd-parity method, the value of the parity bit is chosen so that the total number of 1s
in the code group (including the parity bit) is an odd number.
A parity generator is a combination logic system to generate the parity bit at the transmitting
side.
Parity Checker:- The message bits with the parity bit are transmitted to their destination,
where they are applied to a parity checker circuit.
The circuit that checks the parity at the receiver side is called the parity checker.
The parity checker circuit produces a check bit and is very similar to the parity generator
circuit.
If the check bit is 1, then it is assumed that the received data is incorrect. The check bit will
be 0 if the received data is correct.