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Pipelining Seminar

Pipelining is a technique used in CPUs to increase overall performance by allowing multiple instructions to be executed simultaneously. It works by splitting the instruction execution process into discrete stages - fetch, decode, execute, and writeback - that can overlap between different instructions. By ensuring each stage takes one clock cycle or less, a new instruction can enter the pipeline every clock cycle, allowing multiple instructions to be processed at the same time. While pipelining improves throughput, it also introduces hazards like data and control dependencies that can stall the pipeline if not addressed properly.

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27 views

Pipelining Seminar

Pipelining is a technique used in CPUs to increase overall performance by allowing multiple instructions to be executed simultaneously. It works by splitting the instruction execution process into discrete stages - fetch, decode, execute, and writeback - that can overlap between different instructions. By ensuring each stage takes one clock cycle or less, a new instruction can enter the pipeline every clock cycle, allowing multiple instructions to be processed at the same time. While pipelining improves throughput, it also introduces hazards like data and control dependencies that can stall the pipeline if not addressed properly.

Uploaded by

DURAISAMY
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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PIPELINING

-Jeya Sieola J
Pipelining is a particular way of organizing concurrent activity in a
computer system.
Pipelining is a process of arrangement of hardware elements of the
CPU such that its overall performance is increased. Simultaneous
Pipelining execution of more than one instruction takes place in a pipelined
processor.

A processor executes a program by fetching and executing


instructions, one after the other.
• Fi – To Fetch
• Ei – To Execute
• Ii – Instruction

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Now consider a computer that has two separate hardware units, one for
fetching instructions and another for executing them, as shown in Figure 3.2.
The instruction fetched by the fetch unit is deposited in an intermediate storage
buffer, B1. This buffer is needed to enable the execution unit to execute the
instruction while the fetch unit is fetching the next instruction. The results of
execution are deposited in the destination location specified by the instruction.
The data can be operated by the instructions are inside the block labeled
"Execution unit".

An interstage storage buffer, B1 is needed to hold the information being


passed from one stage to the next. New information is loaded into this
buffer at the end of each clock cycle.

Basic idea of instruction pipelining


The computer is controlled by a clock whose period is such that the
fetch and execute steps of any instruction can each be completed in
one clock cycle.

In the first clock cycle, the fetch unit fetches an instruction I1 (step
F1 ) and stores it in buffer Bl at the end of the clock cycle.
In the second clock cycle, the instruction fetch unit proceeds with the
fetch operation for instruction I2 (step F2). Meanwhile, the execution
unit performs the operation specified by instruction I1, which is
available to it in buffer Bl (step E1). By the end of the second clock
cycle, the execution of instruction I1 is completed and instruction I2 is
available. Instruction I2 is stored in B1, replacing I1, which is no
longer needed. Step E2 is performed by the execution unit during the
third clock cycle, while instruction I3 is being fetched by the fetch unit.
In this manner, both the fetch and execute units are kept busy all the
time. 4

Basic idea of instruction pipelining


A pipelined processor may process each instruction in four steps, as follows:

F Fetch: read the instruction from the memory.


D Decode: decode the instruction and fetch the source operand(s).
E Execute: perform the operation specified by the instruction.
W Write: store the result in the destination location.

These units are capable of performing their tasks simultaneously and without interfering
with one another. Information is passed from one unit to the next through the storage
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buffer.
Eg:
During cycle 4
• Buffer B1 holds instruction 3, which is fetched in cycle 3, and it is being
decoded by the instruction-decoding unit.
• Buffer B2 holds both the source operands for instruction I2 and the
specification of the operation to be performed.
• Buffer B3 holds the results produced by the execution unit and the
destination information for instruction I1.

A 4-stage pipeline
Advantages:

•Instruction throughput increases.


•An increase in the number of pipeline stages increases the number of
instructions executed simultaneously.
•Faster ALU can be designed when pipelining is used.
•Pipelined CPU’s works at higher clock frequencies than the RAM.
•Pipelining increases the overall performance of the CPU.

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Disadvantages:

• Designing of the pipelined processor is complex.


• The throughput of a pipelined processor is difficult to predict.
• The longer the pipeline, worse the problem of hazard for branch
instructions.

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By the end of the third clock cycle,
Completed instruction/instructions – I1, I2
Currently processing instruction – I3
Which instruction is present in the buffer-I3
Replaced instruction- I2

Basic idea of instruction pipelining


Data Hazards
A Pipeline Hazard occurs when the pipeline, or some portion of the pipeline,
must stall because conditions do not permit continued execution. Such a
pipeline stall is also referred to as a pipeline hazards
The three different types of hazards in computer architecture are:
• 1. Structural Hazards or resource Hazards
• 2. Data Hazards
• 3. Control Hazards or instruction Hazards

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Data Hazards

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Structural Hazards

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Control Hazards

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THANK YOU!

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